{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:31:25Z","timestamp":1750221085206,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":81,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,10,15]],"date-time":"2018-10-15T00:00:00Z","timestamp":1539561600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"German Federal Ministry of Education and Research","award":["BMBF Grant 16KIS0592K HWSec","BMBF Grant 16KIS0820 emproof"],"award-info":[{"award-number":["BMBF Grant 16KIS0592K HWSec","BMBF Grant 16KIS0820 emproof"]}]},{"name":"European Research Council","award":["ERC Advanced Grant No. 695022 (EPoCH)","ERC Starting Grant No. 640110 (BASTION)"],"award-info":[{"award-number":["ERC Advanced Grant No. 695022 (EPoCH)","ERC Starting Grant No. 640110 (BASTION)"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,10,15]]},"DOI":"10.1145\/3243734.3243861","type":"proceedings-article","created":{"date-parts":[[2018,10,16]],"date-time":"2018-10-16T17:38:33Z","timestamp":1539711513000},"page":"1649-1666","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["An Exploratory Analysis of Microcode as a Building Block for System Defenses"],"prefix":"10.1145","author":[{"given":"Benjamin","family":"Kollenda","sequence":"first","affiliation":[{"name":"Ruhr-Universit\u00e4t Bochum, Bochum, Germany"}]},{"given":"Philipp","family":"Koppe","sequence":"additional","affiliation":[{"name":"Ruhr-Universit\u00e4t Bochum, Bochum, Germany"}]},{"given":"Marc","family":"Fyrbiak","sequence":"additional","affiliation":[{"name":"Ruhr-Universit\u00e4t Bochum, Bochum, Germany"}]},{"given":"Christian","family":"Kison","sequence":"additional","affiliation":[{"name":"Ruhr-Universit\u00e4t Bochum, Bochum, Germany"}]},{"given":"Christof","family":"Paar","sequence":"additional","affiliation":[{"name":"Ruhr-Universit\u00e4t Bochum, Bochum, Germany"}]},{"given":"Thorsten","family":"Holz","sequence":"additional","affiliation":[{"name":"Ruhr-Universit\u00e4t Bochum, Bochum, Germany"}]}],"member":"320","published-online":{"date-parts":[[2018,10,15]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1102120.1102165"},{"key":"e_1_3_2_2_2_1","unstructured":"Advanced Micro Devices Inc. 2005. Software Optimization Guide for AMD64 Processors. 189--200 pages. {Online}. Available: https:\/\/support.amd.com\/TechDocs\/25112.PDF.  Advanced Micro Devices Inc. 2005. Software Optimization Guide for AMD64 Processors. 189--200 pages. {Online}. Available: https:\/\/support.amd.com\/TechDocs\/25112.PDF."},{"key":"e_1_3_2_2_3_1","unstructured":"Advanced Micro Devices Inc. 2013. Revision Guide for AMD Family 16h Models 00h-0Fh Processors.  Advanced Micro Devices Inc. 2013. Revision Guide for AMD Family 16h Models 00h-0Fh Processors."},{"key":"e_1_3_2_2_4_1","volume-title":"International workshop on hardware and architectural support for security and privacy","volume":"13","author":"Anati Ittai","year":"2013","unstructured":"Ittai Anati , Shay Gueron , Simon Johnson , and Vincent Scarlata . 2013 . Innovative technology for CPU based attestation and sealing . In International workshop on hardware and architectural support for security and privacy , Vol. 13 . ACM New York, NY, USA. Ittai Anati, Shay Gueron, Simon Johnson, and Vincent Scarlata. 2013. Innovative technology for CPU based attestation and sealing. In International workshop on hardware and architectural support for security and privacy, Vol. 13. ACM New York, NY, USA."},{"key":"e_1_3_2_2_5_1","unstructured":"Starr Andersen and Vincent Abella. 2004. Changes to Functionality in Microsoft Windows XP Service Pack 2 Part 3: Memory Protection Technologies Data Execution Prevention. {Online}. Available: http:\/\/technet.microsoft.com\/en-us\/library\/bb457155.aspx.  Starr Andersen and Vincent Abella. 2004. Changes to Functionality in Microsoft Windows XP Service Pack 2 Part 3: Memory Protection Technologies Data Execution Prevention. {Online}. Available: http:\/\/technet.microsoft.com\/en-us\/library\/bb457155.aspx."},{"volume-title":"USENIX Security Symposium.","author":"Andriesse Dennis","key":"e_1_3_2_2_6_1","unstructured":"Dennis Andriesse , Xi Chen , Victor van der Veen, Asia Slowinska, and Herbert Bos. 2016. An In-Depth Analysis of Disassembly on Full-Scale x86\/x64 Binaries . In USENIX Security Symposium. Dennis Andriesse, Xi Chen, Victor van der Veen, Asia Slowinska, and Herbert Bos. 2016. An In-Depth Analysis of Disassembly on Full-Scale x86\/x64 Binaries. In USENIX Security Symposium."},{"key":"e_1_3_2_2_7_1","volume-title":"Opteron Exposed: Reverse Engineering AMD K8 Microcode Updates. {Online}. Available: http:\/\/www.securiteam.com\/securityreviews\/5FP0M1PDFO.html.","author":"Anonymous","year":"2004","unstructured":"Anonymous . 2004 . Opteron Exposed: Reverse Engineering AMD K8 Microcode Updates. {Online}. Available: http:\/\/www.securiteam.com\/securityreviews\/5FP0M1PDFO.html. Anonymous. 2004. Opteron Exposed: Reverse Engineering AMD K8 Microcode Updates. {Online}. Available: http:\/\/www.securiteam.com\/securityreviews\/5FP0M1PDFO.html."},{"key":"e_1_3_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2660267.2660378"},{"key":"e_1_3_2_2_9_1","volume-title":"USENIX Security Symposium.","author":"Backes Michael","year":"2014","unstructured":"Michael Backes and Stefan N\u00fcrnberger . 2014 . Oxymoron: making fine-grained memory randomization practical by allowing code sharing . In USENIX Security Symposium. Michael Backes and Stefan N\u00fcrnberger. 2014. Oxymoron: making fine-grained memory randomization practical by allowing code sharing. In USENIX Security Symposium."},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/948109.948147"},{"key":"e_1_3_2_2_11_1","unstructured":"Ben Hawkes. 2013. Notes on Intel Microcode Updates. {Online}. Available: http:\/\/inertiawar.com\/microcode\/.  Ben Hawkes. 2013. Notes on Intel Microcode Updates. {Online}. Available: http:\/\/inertiawar.com\/microcode\/."},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024569.2024572"},{"key":"e_1_3_2_2_13_1","volume-title":"Software Grand Exposure: SGX Cache Attacks Are Practical. In USENIX Workshop on Offensive Technologies (WOOT).","author":"Brasser Ferdinand","year":"2017","unstructured":"Ferdinand Brasser , Urs M\u00fcller , Alexandra Dmitrienko , Kari Kostiainen , Srdjan Capkun , and Ahmad-Reza Sadeghi . 2017 . Software Grand Exposure: SGX Cache Attacks Are Practical. In USENIX Workshop on Offensive Technologies (WOOT). Ferdinand Brasser, Urs M\u00fcller, Alexandra Dmitrienko, Kari Kostiainen, Srdjan Capkun, and Ahmad-Reza Sadeghi. 2017. Software Grand Exposure: SGX Cache Attacks Are Practical. In USENIX Workshop on Offensive Technologies (WOOT)."},{"key":"e_1_3_2_2_14_1","volume-title":"Chen and Gail-Joon Ahn","author":"Daming","year":"2014","unstructured":"Daming D. Chen and Gail-Joon Ahn . 2014 . Security Analysis of x86 Processor Microcode . {Online}. Available: https:\/\/www.dcddcc.com\/docs\/2014_paper_microcode.pdf. Daming D. Chen and Gail-Joon Ahn. 2014. Security Analysis of x86 Processor Microcode. {Online}. Available: https:\/\/www.dcddcc.com\/docs\/2014_paper_microcode.pdf."},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"crossref","unstructured":"Xi Chen Asia Slowinska Dennis Andriesse Herbert Bos and Cristiano Giuffrida. 2015. StackArmor: Comprehensive Protection From Stack-based Memory Error Vulnerabilities for Binaries. In NDSS.  Xi Chen Asia Slowinska Dennis Andriesse Herbert Bos and Cristiano Giuffrida. 2015. StackArmor: Comprehensive Protection From Stack-based Memory Error Vulnerabilities for Binaries. In NDSS.","DOI":"10.14722\/ndss.2015.23248"},{"key":"e_1_3_2_2_16_1","unstructured":"Clang's SafeStack {n. d.}. Clang's SafeStack. http:\/\/clang.llvm.org\/docs\/SafeStack.html.  Clang's SafeStack {n. d.}. Clang's SafeStack. http:\/\/clang.llvm.org\/docs\/SafeStack.html."},{"key":"e_1_3_2_2_17_1","unstructured":"Control-Flow Enforcement Technology Preview 2016. Control-Flow Enforcement Technology Preview. https:\/\/software.intel.com\/sites\/default\/files\/managed\/4d\/2a\/control-flow-enforcement-technology-preview.pdf.  Control-Flow Enforcement Technology Preview 2016. Control-Flow Enforcement Technology Preview. https:\/\/software.intel.com\/sites\/default\/files\/managed\/4d\/2a\/control-flow-enforcement-technology-preview.pdf."},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2015.52"},{"key":"e_1_3_2_2_20_1","unstructured":"CVE Details. {n. d.}. CVSS Score Distribution Reports and Trends Over Time. {Online}. Available: https:\/\/www.cvedetails.com\/cvss-score-charts.php.  CVE Details. {n. d.}. CVSS Score Distribution Reports and Trends Over Time. {Online}. Available: https:\/\/www.cvedetails.com\/cvss-score-charts.php."},{"key":"e_1_3_2_2_21_1","unstructured":"CVE Details. {n. d.}. Insufficient input validation statistics. {Online}. Available: https:\/\/www.cvedetails.com\/vulnerability-list\/opbyp-1\/bypass.html.  CVE Details. {n. d.}. Insufficient input validation statistics. {Online}. Available: https:\/\/www.cvedetails.com\/vulnerability-list\/opbyp-1\/bypass.html."},{"key":"e_1_3_2_2_22_1","unstructured":"CVE Details. {n. d.}. Memory corruption statistics. {Online}. Available: https:\/\/www.cvedetails.com\/vulnerability-list\/opmemc-1\/memory-corruption.html.  CVE Details. {n. d.}. Memory corruption statistics. {Online}. Available: https:\/\/www.cvedetails.com\/vulnerability-list\/opmemc-1\/memory-corruption.html."},{"key":"e_1_3_2_2_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2714576.2714635"},{"key":"e_1_3_2_2_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744847"},{"key":"e_1_3_2_2_25_1","doi-asserted-by":"publisher","DOI":"10.14722\/ndss.2015.23262"},{"key":"e_1_3_2_2_26_1","unstructured":"Discussion for porting SafeStack to GCC {n. d.}. Discussion for porting SafeStack to GCC. https:\/\/gcc.gnu.org\/ml\/gcc\/2016-04\/msg00083.html.  Discussion for porting SafeStack to GCC {n. d.}. Discussion for porting SafeStack to GCC. https:\/\/gcc.gnu.org\/ml\/gcc\/2016-04\/msg00083.html."},{"key":"e_1_3_2_2_27_1","volume-title":"CacheAudit: A Tool for the Static Analysis of Cache Side Channels. In USENIX Security Symposium.","author":"Doychev Goran","year":"2013","unstructured":"Goran Doychev , Dominik Feld , Boris K\u00f6pf , Laurent Mauborgne , and Jan Reineke . 2013 . CacheAudit: A Tool for the Static Analysis of Cache Side Channels. In USENIX Security Symposium. Goran Doychev, Dominik Feld, Boris K\u00f6pf, Laurent Mauborgne, and Jan Reineke. 2013. CacheAudit: A Tool for the Static Analysis of Cache Side Channels. In USENIX Security Symposium."},{"key":"e_1_3_2_2_28_1","unstructured":"DynamoRIO contributors. {n. d.}. DynamoRIO Dynamic Instrumentation Tool Platform. {Online}. Available: http:\/\/www.dynamorio.org\/.  DynamoRIO contributors. {n. d.}. DynamoRIO Dynamic Instrumentation Tool Platform. {Online}. Available: http:\/\/www.dynamorio.org\/."},{"key":"e_1_3_2_2_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2015.53"},{"key":"e_1_3_2_2_30_1","unstructured":"John G. Favor. 2002. RISC86 INSTRUCTION SET. http:\/\/www.google.com\/patents\/US6336178 US Patent 6 336 178.  John G. Favor. 2002. RISC86 INSTRUCTION SET. http:\/\/www.google.com\/patents\/US6336178 US Patent 6 336 178."},{"key":"e_1_3_2_2_31_1","unstructured":"FortiGuard SE Team. 2018. Meltdown\/Spectre Update | Fortinet Blog. {Online}. Available: https:\/\/blog.fortinet.com\/2018\/01\/30\/the-exponential-growth-of-detected-malware-targeted-at-meltdown-and-spectre.  FortiGuard SE Team. 2018. Meltdown\/Spectre Update | Fortinet Blog. {Online}. Available: https:\/\/blog.fortinet.com\/2018\/01\/30\/the-exponential-growth-of-detected-malware-targeted-at-meltdown-and-spectre."},{"key":"e_1_3_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2664243.2664249"},{"key":"e_1_3_2_2_33_1","doi-asserted-by":"crossref","unstructured":"Robert Gawlik Benjamin Kollenda Philipp Koppe Behrad Garmany and Thorsten Holz. 2016. Enabling Client-Side Crash-Resistance to Overcome Diversification and Information Hiding. In NDSS.  Robert Gawlik Benjamin Kollenda Philipp Koppe Behrad Garmany and Thorsten Holz. 2016. Enabling Client-Side Crash-Resistance to Overcome Diversification and Information Hiding. In NDSS.","DOI":"10.14722\/ndss.2016.23262"},{"key":"e_1_3_2_2_34_1","volume-title":"25th USENIX Security Symposium (USENIX Security 16)","author":"G\u00f6ktas Enes","year":"2016","unstructured":"Enes G\u00f6ktas , Robert Gawlik , Benjamin Kollenda , E Athanasopoulos , G Portokalidis , C Giuffrida , and H Bos . 2016 . Undermining information hiding (and what to do about it) . In 25th USENIX Security Symposium (USENIX Security 16) . 105--119. Enes G\u00f6ktas, Robert Gawlik, Benjamin Kollenda, E Athanasopoulos, G Portokalidis, C Giuffrida, and H Bos. 2016. Undermining information hiding (and what to do about it). In 25th USENIX Security Symposium (USENIX Security 16). 105--119."},{"key":"e_1_3_2_2_35_1","volume-title":"ASLR on the Line: Practical Cache Attacks on the MMU. In Symposium on Network and Distributed System Security (NDSS).","author":"Gras Ben","year":"2017","unstructured":"Ben Gras , Kaveh Razavi , Erik Bosman , Herbert Bos , and Christiano Giuffrida . 2017 . ASLR on the Line: Practical Cache Attacks on the MMU. In Symposium on Network and Distributed System Security (NDSS). Ben Gras, Kaveh Razavi, Erik Bosman, Herbert Bos, and Christiano Giuffrida. 2017. ASLR on the Line: Practical Cache Attacks on the MMU. In Symposium on Network and Distributed System Security (NDSS)."},{"key":"e_1_3_2_2_36_1","volume-title":"W3C Recommendation","author":"Grigorik Ilya","year":"2012","unstructured":"Ilya Grigorik , James Simonsen , and Jatinder Mann . 2017. W3C Recommendation 17 December 2012 . https:\/\/www.w3.org\/TR\/2017\/CR-hr-time-2--20170803\/#dom-domhighrestimestamp. Ilya Grigorik, James Simonsen, and Jatinder Mann. 2017. W3C Recommendation 17 December 2012. https:\/\/www.w3.org\/TR\/2017\/CR-hr-time-2--20170803\/#dom-domhighrestimestamp."},{"key":"e_1_3_2_2_37_1","volume-title":"Project Zero: Reading privileged memory with a side-channel. {Online}. Available: https:\/\/googleprojectzero.blogspot.co.at\/2018\/01\/reading-privileged-memory-with-side.html.","author":"Horn Jann","year":"2018","unstructured":"Jann Horn . 2018 . Project Zero: Reading privileged memory with a side-channel. {Online}. Available: https:\/\/googleprojectzero.blogspot.co.at\/2018\/01\/reading-privileged-memory-with-side.html. Jann Horn. 2018. Project Zero: Reading privileged memory with a side-channel. {Online}. Available: https:\/\/googleprojectzero.blogspot.co.at\/2018\/01\/reading-privileged-memory-with-side.html."},{"key":"e_1_3_2_2_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1134760.1134764"},{"key":"e_1_3_2_2_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2013.23"},{"volume-title":"6th Generation Intel\u00ae Processor Family Specification Update","author":"Intel Corporation","key":"e_1_3_2_2_40_1","unstructured":"Intel Corporation . 2016. 6th Generation Intel\u00ae Processor Family Specification Update . Intel Corporation. 2016. 6th Generation Intel\u00ae Processor Family Specification Update."},{"key":"e_1_3_2_2_41_1","unstructured":"Intel Corporation. 2017. Intel Issues Updates to Protect Systems from Security Exploits. {Online}. Available: https:\/\/newsroom.intel.com\/news-releases\/intel-issues-updates-protect-systems-security-exploits\/.  Intel Corporation. 2017. Intel Issues Updates to Protect Systems from Security Exploits. {Online}. Available: https:\/\/newsroom.intel.com\/news-releases\/intel-issues-updates-protect-systems-security-exploits\/."},{"key":"e_1_3_2_2_42_1","unstructured":"Intel Corporation. 2017. Microcode Revision Guidance. {Online}. Available: https:\/\/newsroom.intel.com\/wp-content\/uploads\/sites\/11\/2018\/01\/microcode-update-guidance.pdf.  Intel Corporation. 2017. Microcode Revision Guidance. {Online}. Available: https:\/\/newsroom.intel.com\/wp-content\/uploads\/sites\/11\/2018\/01\/microcode-update-guidance.pdf."},{"key":"e_1_3_2_2_43_1","unstructured":"Intel Corporation. 2018. Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual. 2809 pages.  Intel Corporation. 2018. Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual. 2809 pages."},{"key":"e_1_3_2_2_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/948109.948146"},{"key":"e_1_3_2_2_45_1","volume-title":"Spectre Attacks: Exploiting Speculative Execution. ArXiv e-prints","author":"Kocher Paul","year":"2018","unstructured":"Paul Kocher , Daniel Genkin , Daniel Gruss , Werner Haas , Mike Hamburg , Moritz Lipp , Stefan Mangard , Thomas Prescher , Michael Schwarz , and Yuval Yarom . 2018 . Spectre Attacks: Exploiting Speculative Execution. ArXiv e-prints (2018). Paul Kocher, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2018. Spectre Attacks: Exploiting Speculative Execution. ArXiv e-prints (2018)."},{"key":"e_1_3_2_2_46_1","doi-asserted-by":"crossref","unstructured":"Paul C. Kocher. 1996. Timing Attacks on Implementations of Diffie-Hellman RSA DSS and Other Systems. In CRYPTO. 104--113.   Paul C. Kocher. 1996. Timing Attacks on Implementations of Diffie-Hellman RSA DSS and Other Systems. In CRYPTO. 104--113.","DOI":"10.1007\/3-540-68697-5_9"},{"key":"e_1_3_2_2_47_1","volume-title":"Trusted Browsers for Uncertain Times. In USENIX Security Symposium. 463--480","author":"Kohlbrenner David","year":"2016","unstructured":"David Kohlbrenner and Hovav Shacham . 2016 . Trusted Browsers for Uncertain Times. In USENIX Security Symposium. 463--480 . David Kohlbrenner and Hovav Shacham. 2016. Trusted Browsers for Uncertain Times. In USENIX Security Symposium. 463--480."},{"key":"e_1_3_2_2_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2017.58"},{"key":"e_1_3_2_2_49_1","volume-title":"USENIX Security Symposium.","author":"Koppe Philipp","year":"2017","unstructured":"Philipp Koppe , Benjamin Kollenda , Marc Fyrbiak , Christian Kison , Robert Gawlik , Christof Paar , and Thorsten Holz . 2017 . Reverse Engineering x86 Processor Microcode . In USENIX Security Symposium. Philipp Koppe, Benjamin Kollenda, Marc Fyrbiak, Christian Kison, Robert Gawlik, Christof Paar, and Thorsten Holz. 2017. Reverse Engineering x86 Processor Microcode. In USENIX Security Symposium."},{"key":"e_1_3_2_2_50_1","volume-title":"Code-Pointer Integrity. In Symposium on Operating Systems Design and Implementation (OSDI)","volume":"14","author":"Kuznetsov Volodymyr","year":"2014","unstructured":"Volodymyr Kuznetsov , Laszlo Szekeres , Mathias Payer , George Candea , R Sekar , and Dawn Song . 2014 . Code-Pointer Integrity. In Symposium on Operating Systems Design and Implementation (OSDI) , Vol. 14 . Volodymyr Kuznetsov, Laszlo Szekeres, Mathias Payer, George Candea, R Sekar, and Dawn Song. 2014. Code-Pointer Integrity. In Symposium on Operating Systems Design and Implementation (OSDI), Vol. 14."},{"key":"e_1_3_2_2_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452024"},{"key":"e_1_3_2_2_52_1","volume-title":"USENIX Security Symposium. 16--18","author":"Lee Sangho","year":"2017","unstructured":"Sangho Lee , Ming-Wei Shih , Prasun Gera , Taesoo Kim , Hyesoon Kim , and Marcus Peinado . 2017 . Inferring fine-grained control flow inside SGX enclaves with branch shadowing . In USENIX Security Symposium. 16--18 . Sangho Lee, Ming-Wei Shih, Prasun Gera, Taesoo Kim, Hyesoon Kim, and Marcus Peinado. 2017. Inferring fine-grained control flow inside SGX enclaves with branch shadowing. In USENIX Security Symposium. 16--18."},{"key":"e_1_3_2_2_53_1","volume-title":"ArXiv e-prints","author":"Lipp Moritz","year":"2018","unstructured":"Moritz Lipp , Michael Schwarz , Daniel Gruss , Thomas Prescher , Werner Haas , Stefan Mangard , Paul Kocher , Daniel Genkin , Yuval Yarom , and Mike Hamburg . 2018. Meltdown. ArXiv e-prints ( 2018 ). Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown. ArXiv e-prints (2018)."},{"key":"e_1_3_2_2_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/2810103.2813694"},{"key":"e_1_3_2_2_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/1064978.1065034"},{"key":"e_1_3_2_2_56_1","volume-title":"Pickett","author":"McGrath Kevin J.","year":"2002","unstructured":"Kevin J. McGrath and James K . Pickett . 2002 . MICROCODE PATCH DEVICE. http:\/\/www.google.com\/patents\/US6438664 US Patent 6,438,664. Kevin J. McGrath and James K. Pickett. 2002. MICROCODE PATCH DEVICE. http:\/\/www.google.com\/patents\/US6438664 US Patent 6,438,664."},{"key":"e_1_3_2_2_57_1","unstructured":"Microprograms. {n. d.}. {Online}. Available: https:\/\/github.com\/RUB-SysSec\/Microcode.  Microprograms. {n. d.}. {Online}. Available: https:\/\/github.com\/RUB-SysSec\/Microcode."},{"key":"e_1_3_2_2_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/1273442.1250746"},{"key":"e_1_3_2_2_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/2810103.2813644"},{"key":"e_1_3_2_2_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/1920261.1920269"},{"key":"e_1_3_2_2_61_1","doi-asserted-by":"publisher","DOI":"10.1145\/2810103.2813708"},{"key":"e_1_3_2_2_62_1","unstructured":"pakt. 2012. Leaking information with timing attacks on hashtables.  pakt. 2012. Leaking information with timing attacks on hashtables."},{"key":"e_1_3_2_2_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516670"},{"key":"e_1_3_2_2_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2012.41"},{"key":"e_1_3_2_2_65_1","unstructured":"PaX Team. 2003. Address Space Layout Randomization (ASLR). {Online}. Available: pax.grsecurity.net\/docs\/aslr.txt.  PaX Team. 2003. Address Space Layout Randomization (ASLR). {Online}. Available: pax.grsecurity.net\/docs\/aslr.txt."},{"key":"e_1_3_2_2_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/1920261.1920268"},{"key":"e_1_3_2_2_67_1","volume-title":"USENIX Windows NT Workshop.","author":"Romer Ted","year":"1997","unstructured":"Ted Romer , Geoff Voelker , Dennis Lee , Alec Wolman , Wayne Wong , Hank Levy , Brian Bershad , and Brad Chen . 1997 . Instrumentation and optimization of Win32\/Intel executables using Etch . In USENIX Windows NT Workshop. Ted Romer, Geoff Voelker, Dennis Lee, Alec Wolman, Wayne Wong, Hank Levy, Brian Bershad, and Brad Chen. 1997. Instrumentation and optimization of Win32\/Intel executables using Etch. In USENIX Windows NT Workshop."},{"key":"e_1_3_2_2_68_1","volume-title":"IEEE Workshop on Compiler and Architectural Techniques for Application Reliability and Security (CATARS).","author":"Salamat Babak","year":"2008","unstructured":"Babak Salamat , Andreas Gal , and Michael Franz . 2008 . Reverse stack execution in a multi-variant execution environment . In IEEE Workshop on Compiler and Architectural Techniques for Application Reliability and Security (CATARS). Babak Salamat, Andreas Gal, and Michael Franz. 2008. Reverse stack execution in a multi-variant execution environment. In IEEE Workshop on Compiler and Architectural Techniques for Application Reliability and Security (CATARS)."},{"key":"e_1_3_2_2_69_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-70972-7_13"},{"key":"e_1_3_2_2_70_1","volume-title":"AddressSanitizer: A Fast Address Sanity Checker. In USENIX Annual Technical Conference.","author":"Serebryany Konstantin","year":"2012","unstructured":"Konstantin Serebryany , Derek Bruening , Alexander Potapenko , and Dmitry Vyukov . 2012 . AddressSanitizer: A Fast Address Sanity Checker. In USENIX Annual Technical Conference. Konstantin Serebryany, Derek Bruening, Alexander Potapenko, and Dmitry Vyukov. 2012. AddressSanitizer: A Fast Address Sanity Checker. In USENIX Annual Technical Conference."},{"key":"e_1_3_2_2_71_1","unstructured":"Konstantin Serebryany Derek Bruening Alexander Potapenko and Dmitry Vyukov. 2015. Address Sanitizer In Hardware. {Online}. Available: https:\/\/github.com\/google\/sanitizers\/wiki\/AddressSanitizerInHardware.  Konstantin Serebryany Derek Bruening Alexander Potapenko and Dmitry Vyukov. 2015. Address Sanitizer In Hardware. {Online}. Available: https:\/\/github.com\/google\/sanitizers\/wiki\/AddressSanitizerInHardware."},{"key":"e_1_3_2_2_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2017.7951732"},{"key":"e_1_3_2_2_73_1","volume-title":"The Effectiveness of Instruction Set Randomization. In USENIX Security Symposium.","author":"Sovarel Ana Nora","year":"2005","unstructured":"Ana Nora Sovarel , David Evans , and Nathanael Paul . 2005 . Where's the FEEB? The Effectiveness of Instruction Set Randomization. In USENIX Security Symposium. Ana Nora Sovarel, David Evans, and Nathanael Paul. 2005. Where's the FEEB? The Effectiveness of Instruction Set Randomization. In USENIX Security Symposium."},{"key":"e_1_3_2_2_74_1","volume-title":"Computer Organization and Architecture: Designing for Performance","author":"Stallings William","unstructured":"William Stallings . 2005. Computer Organization and Architecture: Designing for Performance ( 7 th Edition). Prentice-Hall, Inc. William Stallings. 2005. Computer Organization and Architecture: Designing for Performance (7th Edition). Prentice-Hall, Inc.","edition":"7"},{"key":"e_1_3_2_2_75_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2013.13"},{"key":"e_1_3_2_2_76_1","unstructured":"Arrigo Triulzi. 2015. Pneumonia Shardan Antibiotics and Nasty MOV: a Dead Hand's Tale. {Online}. Available: https:\/\/www.troopers.de\/events\/troopers15\/449_pneumonia_shardan_antibiotics_and_nasty_mov_a_dead_hands_tale\/.  Arrigo Triulzi. 2015. Pneumonia Shardan Antibiotics and Nasty MOV: a Dead Hand's Tale. {Online}. Available: https:\/\/www.troopers.de\/events\/troopers15\/449_pneumonia_shardan_antibiotics_and_nasty_mov_a_dead_hands_tale\/."},{"key":"e_1_3_2_2_77_1","unstructured":"Arrigo Triulzi. 2016. The Chimaera Processor. {Online}. Available: https:\/\/www.troopers.de\/events\/troopers16\/655_the_chimaera_processor\/.  Arrigo Triulzi. 2016. The Chimaera Processor. {Online}. Available: https:\/\/www.troopers.de\/events\/troopers16\/655_the_chimaera_processor\/."},{"key":"e_1_3_2_2_78_1","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3134026"},{"key":"e_1_3_2_2_79_1","volume-title":"USENIX Security Symposium.","author":"Wang Shuai","year":"2015","unstructured":"Shuai Wang , Pei Wang , and Dinghao Wu . 2015 . Reassembleable Disassembling .. In USENIX Security Symposium. Shuai Wang, Pei Wang, and Dinghao Wu. 2015. Reassembleable Disassembling.. In USENIX Security Symposium."},{"key":"e_1_3_2_2_80_1","doi-asserted-by":"publisher","DOI":"10.1145\/2382196.2382216"},{"key":"e_1_3_2_2_81_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-58108-1_16"},{"key":"e_1_3_2_2_82_1","unstructured":"Working Intel CET Bits Now Land In GCC8 2017. Working Intel CET Bits Now Land In GCC8. https:\/\/www.phoronix.com\/scan.php?page=news_item&px=Intel-CET-Working-GCC8.  Working Intel CET Bits Now Land In GCC8 2017. Working Intel CET Bits Now Land In GCC8. https:\/\/www.phoronix.com\/scan.php?page=news_item&px=Intel-CET-Working-GCC8."}],"event":{"name":"CCS '18: 2018 ACM SIGSAC Conference on Computer and Communications Security","sponsor":["SIGSAC ACM Special Interest Group on Security, Audit, and Control"],"location":"Toronto Canada","acronym":"CCS '18"},"container-title":["Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3243734.3243861","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3243734.3243861","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T00:57:47Z","timestamp":1750208267000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3243734.3243861"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10,15]]},"references-count":81,"alternative-id":["10.1145\/3243734.3243861","10.1145\/3243734"],"URL":"https:\/\/doi.org\/10.1145\/3243734.3243861","relation":{},"subject":[],"published":{"date-parts":[[2018,10,15]]},"assertion":[{"value":"2018-10-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}