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Syst."],"published-print":{"date-parts":[[2018,7,31]]},"abstract":"<jats:p>3D stacking of integrated circuits (ICs) provides significant advantages in saving device footprints, improving power management, and continuing performance enhancement, particularly for many-core systems. However, the stacked structure makes the heat dissipation a challenging issue. While Thermal Through Silicon Via (TTSV) is a promising way of lowering the thermal resistance of dies, past research has either overestimated or underestimated the effects of TTSVs as a consequence of the lack of detailed 3D IC models or system-level simulations. Here, we propose a simulation flow to accurately simulate TTSV effects on 3D ICs. We adopt benchmarks from Splash-2 running on a full-system mode of the gem5 simulator, which generates all the system component activities. McPAT is used to generate the corresponding power consumption and the power traces are fed to HotSpot for thermal simulation. The temperature profiles of 2D and 3D Nehalem-like \u00d786 processors are compared. TTSVs are later placed close to hotspot regions to facilitate heat dissipation; the peak temperature of 3D Nehalem is reduced by 5--25% with a small area overhead of 6%. By using a detailed 3D thermal model, full-system simulation, and a validated thermal simulator, our results show accurate thermal analysis of 3D ICs.<\/jats:p>","DOI":"10.1145\/3264736","type":"journal-article","created":{"date-parts":[[2018,10,24]],"date-time":"2018-10-24T11:57:18Z","timestamp":1540382238000},"page":"1-16","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["System-Level Analysis of 3D ICs with Thermal TSVs"],"prefix":"10.1145","volume":"14","author":[{"given":"Ayed","family":"Alqahtani","sequence":"first","affiliation":[{"name":"University of California, Irvine"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zongqing","family":"Ren","sequence":"additional","affiliation":[{"name":"University of California, Irvine"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaeho","family":"Lee","sequence":"additional","affiliation":[{"name":"University of California, Irvine"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nader","family":"Bagherzadeh","sequence":"additional","affiliation":[{"name":"University of California, Irvine"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,10,23]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124547"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1115\/1.4005708"},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","unstructured":"E. Beyne etal 2008. Through-silicon via and die stacking technologies for microsystems- integration. In Technical Digest -- International Electron Devices Meeting (IEDM).  E. Beyne et al. 2008. Through-silicon via and die stacking technologies for microsystems- integration. In Technical Digest -- International Electron Devices Meeting (IEDM).","DOI":"10.1109\/IEDM.2008.4796734"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2014.6838582"},{"volume-title":"Three Dimensional System Integration: IC Stacking Process and Design","author":"Burns J.","key":"e_1_2_1_7_1","unstructured":"J. Burns . 2011. TSV-based 3D integration . In Three Dimensional System Integration: IC Stacking Process and Design . Springer , 13--32. J. Burns. 2011. TSV-based 3D integration. In Three Dimensional System Integration: IC Stacking Process and Design. Springer, 13--32."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2009.0127"},{"volume-title":"Proceedings of the 15th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm\u201916)","author":"Chen C. P.","key":"e_1_2_1_10_1","unstructured":"C. P. Chen , Y. Weng , and G. Subbarayan . 2016. Topology optimization for efficient heat removal in 3D packages . In Proceedings of the 15th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm\u201916) , 238--244. C. P. Chen, Y. Weng, and G. Subbarayan. 2016. Topology optimization for efficient heat removal in 3D packages. In Proceedings of the 15th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm\u201916), 238--244."},{"volume-title":"Int. Electron Devices Meet. Tech. Dig. (Cat. No. 01CH37224)","author":"Chiang T.-Y. C. T.-Y.","key":"e_1_2_1_11_1","unstructured":"T.-Y. C. T.-Y. Chiang , S. J. Souri , C. O. C. C. O. Chui , and K. C. Saraswat . 2001. Thermal analysis of heterogeneous 3D ICs with various integration scenarios . Int. Electron Devices Meet. Tech. Dig. (Cat. No. 01CH37224) , 681--684. T.-Y. C. T.-Y. Chiang, S. J. Souri, C. O. C. C. O. Chui, and K. C. Saraswat. 2001. Thermal analysis of heterogeneous 3D ICs with various integration scenarios. Int. Electron Devices Meet. Tech. Dig. (Cat. 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In Proceedings of the Annual IEEE Semiconductor Thermal Measurement and Management Symposium, 23--28."},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design -- Digest of Technical Papers (ICCAD\u201905)","author":"Cong J.","key":"e_1_2_1_15_1","unstructured":"J. Cong and Y. Zhang . 2005. Thermal via planning for 3-D ICs . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design -- Digest of Technical Papers (ICCAD\u201905) , 744--751. J. Cong and Y. Zhang. 2005. Thermal via planning for 3-D ICs. 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Charlottesville."}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3264736","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3264736","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:10:54Z","timestamp":1750212654000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3264736"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7,31]]},"references-count":41,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2018,7,31]]}},"alternative-id":["10.1145\/3264736"],"URL":"https:\/\/doi.org\/10.1145\/3264736","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2018,7,31]]},"assertion":[{"value":"2017-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-10-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}