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We present the detailed ADC architecture and a step-by-step process for designing the zoom-ADC. The design flow does not rely on the extensive knowledge of an experienced ADC designer. Two ADCs have been synthesized with different performance requirements in the 65nm CMOS process. The first ADC achieves a 90.4dB Signal-to-Noise Ratio (SNR) in 512\u03bcs measurement time and consumes 17\u03bcW power. The second design achieves a 78.2dB SNR in 31.25\u03bcs measurement time and consumes 63\u03bcW power.<\/jats:p>","DOI":"10.1145\/3266227","type":"journal-article","created":{"date-parts":[[2018,12,21]],"date-time":"2018-12-21T13:39:21Z","timestamp":1545399561000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Knowledge- and Simulation-Based Synthesis of Area-Efficient Passive Loop Filter Incremental Zoom-ADC for Built-In Self-Test Applications"],"prefix":"10.1145","volume":"24","author":[{"given":"Osman Emir","family":"Erol","sequence":"first","affiliation":[{"name":"Arizona State University, Tempe, AZ"}]},{"given":"Sule","family":"Ozev","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ"}]}],"member":"320","published-online":{"date-parts":[[2018,12,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.711312"},{"volume-title":"Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them, Washington DC. 805--814","author":"Toner M. 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