{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,14]],"date-time":"2026-05-14T22:42:21Z","timestamp":1778798541997,"version":"3.51.4"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2018,12,31]],"date-time":"2018-12-31T00:00:00Z","timestamp":1546214400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1453378,1512937"],"award-info":[{"award-number":["1453378,1512937"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["D15AP00096"],"award-info":[{"award-number":["D15AP00096"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2018,12,31]]},"abstract":"<jats:p>Modern FPGA synthesis tools typically apply a predetermined sequence of logic optimizations on the input logic network before carrying out technology mapping. While the \u201cknown recipes\u201d of logic transformations often lead to improved mapping results, there remains a nontrivial gap between the quality metrics driving the pre-mapping logic optimizations and those targeted by the actual technology mapping. Needless to mention, such miscorrelations would eventually result in suboptimal quality of results.<\/jats:p>\n          <jats:p>In this article, we propose PIMap, which couples logic transformations and technology mapping under an iterative improvement framework for LUT-based FPGAs. In each iteration, PIMap randomly proposes a transformation on the given logic network from an ensemble of candidate optimizations; it then invokes technology mapping and makes use of the mapping result to determine the likelihood of accepting the proposed transformation. By adjusting the optimization objective and incorporating required time constraints during the iterative process, PIMap can flexibly optimize for different objectives including area minimization, delay optimization, and delay-constrained area reduction. To mitigate the runtime overhead, we further introduce parallelization techniques to decompose a large design into multiple smaller sub-netlists that can be optimized simultaneously. Experimental results show that PIMap achieves promising quality improvement over a set of commonly used benchmarks, including improving the majority of the best-known area and delay records for the EPFL benchmark suite.<\/jats:p>","DOI":"10.1145\/3268344","type":"journal-article","created":{"date-parts":[[2019,1,7]],"date-time":"2019-01-07T13:42:28Z","timestamp":1546868548000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["PIMap"],"prefix":"10.1145","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8538-686X","authenticated-orcid":false,"given":"Gai","family":"Liu","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Cornell University, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiru","family":"Zhang","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Cornell University, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,1,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the International Workshop on Logic 8 Synthesis (IWLS\u201915)","author":"Amar\u00fa Luca","year":"2015","unstructured":"Luca Amar\u00fa , Pierre-Emmanuel Gaillardon , and Giovanni De Micheli . 2015 . The EPFL combinational benchmark suite . In Proceedings of the International Workshop on Logic 8 Synthesis (IWLS\u201915) . Luca Amar\u00fa, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. 2015. The EPFL combinational benchmark suite. In Proceedings of the International Workshop on Logic 8 Synthesis (IWLS\u201915)."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2488484"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/3199700.3199747"},{"key":"e_1_2_1_5_1","volume-title":"Release 60413.","author":"Berkeley Logic Synthesis and Verification Group","year":"2017","unstructured":"Berkeley Logic Synthesis and Verification Group , ABC: A System for Sequential Synthesis and Verification , Release 60413. 2017 . Retrieved from http:\/\/www.eecs.berkeley.edu\/&sim;alanmi\/abc\/. Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, Release 60413. 2017. Retrieved from http:\/\/www.eecs.berkeley.edu\/&sim;alanmi\/abc\/."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270327"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1561\/1000000003"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.33"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811447"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.62792"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.329262"},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the International Workshop on Logic 8 Synthesis (IWLS\u201910)","author":"Fi\u0161er Petr","year":"2010","unstructured":"Petr Fi\u0161er and Jan Schmidt . 2010 . It is better to run iterative resynthesis on parts of the circuit . In Proceedings of the International Workshop on Logic 8 Synthesis (IWLS\u201910) . Petr Fi\u0161er and Jan Schmidt. 2010. It is better to run iterative resynthesis on parts of the circuit. In Proceedings of the International Workshop on Logic 8 Synthesis (IWLS\u201910)."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2012.6219019"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2010.5491755"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1214\/ss\/1177011137"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1093\/biomet\/57.1.97"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391478"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/CCECE.2011.6030453"},{"key":"e_1_2_1_19_1","volume-title":"Vecchi","author":"Kirkpatrick Scott","year":"1983","unstructured":"Scott Kirkpatrick , C. Daniel Gelatt , and Mario P . Vecchi . 1983 . Optimization by simmulated annealing. Science 220, 4598 (1983), 671--680. Scott Kirkpatrick, C. Daniel Gelatt, and Mario P. Vecchi. 1983. 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