{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,2]],"date-time":"2026-09-02T06:26:30Z","timestamp":1788330390105,"version":"build-2803163510"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"OOPSLA","license":[{"start":{"date-parts":[[2018,10,24]],"date-time":"2018-10-24T00:00:00Z","timestamp":1540339200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/100011030","name":"U.S. Department of Energy","doi-asserted-by":"publisher","award":["DE-SC0008923"],"award-info":[{"award-number":["DE-SC0008923"]}],"id":[{"id":"10.13039\/100011030","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100015599","name":"Toyota Research Institute","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100015599","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["FA8750-17-2-0126"],"award-info":[{"award-number":["FA8750-17-2-0126"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Application Driving Architectures Research Center"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Proc. ACM Program. Lang."],"published-print":{"date-parts":[[2018,10,24]]},"abstract":"<jats:p>Modern microprocessors are equipped with single instruction multiple data (SIMD) or vector instruction sets which allow compilers to exploit superword level parallelism (SLP), a type of fine-grained parallelism. Current SLP auto-vectorization techniques use heuristics to discover vectorization opportunities in high-level language code. These heuristics are fragile, local and typically only present one vectorization strategy that is either accepted or rejected by a cost model. We present goSLP, a novel SLP auto-vectorization framework which solves the statement packing problem in a pairwise optimal manner. Using an integer linear programming (ILP) solver, goSLP searches the entire space of statement packing opportunities for a whole function at a time, while limiting total compilation time to a few minutes. Furthermore, goSLP optimally solves the vector permutation selection problem using dynamic programming. We implemented goSLP in the LLVM compiler infrastructure, achieving a geometric mean speedup of 7.58% on SPEC2017fp, 2.42% on SPEC2006fp and 4.07% on NAS benchmarks compared to LLVM\u2019s existing SLP auto-vectorizer.<\/jats:p>","DOI":"10.1145\/3276480","type":"journal-article","created":{"date-parts":[[2018,10,24]],"date-time":"2018-10-24T11:57:18Z","timestamp":1540382238000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":30,"title":["goSLP: globally optimized superword level parallelism framework"],"prefix":"10.1145","volume":"2","author":[{"given":"Charith","family":"Mendis","sequence":"first","affiliation":[{"name":"Massachusetts Institute of Technology, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Saman","family":"Amarasinghe","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2018,10,24]]},"reference":[{"key":"e_1_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/29873.29875"},{"key":"e_1_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/378795.378854"},{"key":"e_1_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2908080.2908111"},{"key":"e_1_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1757112.1757140"},{"key":"e_1_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.38"},{"key":"e_1_2_2_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2151024.2151043"},{"key":"e_1_2_2_7_1","doi-asserted-by":"crossref","unstructured":"Chia-Ming Chang Chien-Ming Chen and Chung-Ta King. 1997. Using integer linear programming for instruction scheduling and register allocation in multi-issue processors. Computers &amp; Mathematics with Applications 34 9 (1997) 1 \u2013 14.  Chia-Ming Chang Chien-Ming Chen and Chung-Ta King. 1997. Using integer linear programming for instruction scheduling and register allocation in multi-issue processors. Computers &amp; Mathematics with Applications 34 9 (1997) 1 \u2013 14.","DOI":"10.1016\/S0898-1221(97)00184-3"},{"key":"e_1_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/996841.996853"},{"key":"e_1_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_2_2_10_1","unstructured":"IBM. 2006. PowerPC microprocessor family: Vector\/SIMD multimedia extension technology programming environments manual. IBM Systems and Technology Group (2006).  IBM. 2006. PowerPC microprocessor family: Vector\/SIMD multimedia extension technology programming environments manual. IBM Systems and Technology Group (2006)."},{"key":"e_1_2_2_11_1","unstructured":"IBM. 2017. IBM CPLEX ILP solver. https:\/\/www- 01.ibm.com\/software\/commerce\/optimization\/cplex- optimizer\/  IBM. 2017. IBM CPLEX ILP solver. https:\/\/www- 01.ibm.com\/software\/commerce\/optimization\/cplex- optimizer\/"},{"key":"e_1_2_2_12_1","unstructured":"Intel. 2017a. Intel Software Developer\u2019s manuals. https:\/\/www.intel.com\/content\/www\/us\/en\/architecture- and- technology\/ 64- ia- 32- architectures- software- developer- manual- 325462.html  Intel. 2017a. Intel Software Developer\u2019s manuals. https:\/\/www.intel.com\/content\/www\/us\/en\/architecture- and- technology\/ 64- ia- 32- architectures- software- developer- manual- 325462.html"},{"key":"e_1_2_2_13_1","unstructured":"Intel. 2017b. Intel VTune Amplifier. https:\/\/software.intel.com\/en- us\/intel- vtune- amplifier- xe  Intel. 2017b. Intel VTune Amplifier. https:\/\/software.intel.com\/en- us\/intel- vtune- amplifier- xe"},{"key":"e_1_2_2_14_1","volume-title":"Whole-function Vectorization. In Proceedings of the 9th Annual IEEE\/ACM International Symposium on Code Generation and Optimization (CGO \u201911)","author":"Karrenberg Ralf","year":"2011"},{"key":"e_1_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2491956.2462187"},{"key":"e_1_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065910.1065931"},{"key":"e_1_2_2_17_1","doi-asserted-by":"crossref","unstructured":"Samuel Larsen. 2000. Exploiting Superword Level Parallelism with Multimedia Instruction Sets. S.M. Thesis. Massachusetts Institute of Technology Cambridge MA. http:\/\/groups.csail.mit.edu\/commit\/papers\/00\/SLarsen- SM.pdf  Samuel Larsen. 2000. Exploiting Superword Level Parallelism with Multimedia Instruction Sets. S.M. Thesis. Massachusetts Institute of Technology Cambridge MA. http:\/\/groups.csail.mit.edu\/commit\/papers\/00\/SLarsen- SM.pdf","DOI":"10.1145\/349299.349320"},{"key":"e_1_2_2_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/349299.349320"},{"key":"e_1_2_2_19_1","volume-title":"Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT \u201902)","author":"Larsen Samuel"},{"key":"e_1_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343679"},{"key":"e_1_2_2_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2854038.2854046"},{"key":"e_1_2_2_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2254064.2254106"},{"key":"e_1_2_2_23_1","unstructured":"LLVM. 2017. LLVM Compiler Infrastructure. https:\/\/llvm.org  LLVM. 2017. LLVM Compiler Infrastructure. https:\/\/llvm.org"},{"key":"e_1_2_2_24_1","unstructured":"Roberto Casta\u00f1eda Lozano Mats Carlsson Gabriel Hjort Blindell and Christian Schulte. 2018. Combinatorial Register Allocation and Instruction Scheduling. CoRR abs\/1804.02452 (2018). arXiv: 1804.02452 http:\/\/arxiv.org\/abs\/1804.02452  Roberto Casta\u00f1eda Lozano Mats Carlsson Gabriel Hjort Blindell and Christian Schulte. 2018. Combinatorial Register Allocation and Instruction Scheduling. CoRR abs\/1804.02452 (2018). arXiv: 1804.02452 http:\/\/arxiv.org\/abs\/1804.02452"},{"key":"e_1_2_2_25_1","volume-title":"Ithemal: Accurate, Portable and Fast Basic Block Throughput Estimation using Deep Neural Networks. ArXiv e-prints (Aug.","author":"Mendis Charith","year":"2018"},{"key":"e_1_2_2_26_1","doi-asserted-by":"publisher","DOI":"10.1561\/0400000002"},{"key":"e_1_2_2_27_1","doi-asserted-by":"crossref","unstructured":"Santosh G. Nagarakatte and R. Govindarajan. 2007. Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation. In Compiler Construction Shriram Krishnamurthi and Martin Odersky (Eds.). Springer Berlin Heidelberg Berlin Heidelberg 126\u2013140.   Santosh G. Nagarakatte and R. Govindarajan. 2007. Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation. In Compiler Construction Shriram Krishnamurthi and Martin Odersky (Eds.). Springer Berlin Heidelberg Berlin Heidelberg 126\u2013140.","DOI":"10.1007\/978-3-540-71229-9_9"},{"key":"e_1_2_2_28_1","unstructured":"Division NASA Advanced Supercomputing. 1991\u20132014. NAS C Benchmark Suite 3.0. https:\/\/github.com\/ benchmark- subsetting\/NPB3.0- omp- C\/  Division NASA Advanced Supercomputing. 1991\u20132014. NAS C Benchmark Suite 3.0. https:\/\/github.com\/ benchmark- subsetting\/NPB3.0- omp- C\/"},{"key":"e_1_2_2_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1133981.1133997"},{"key":"e_1_2_2_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454119"},{"key":"e_1_2_2_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.755466"},{"key":"e_1_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.32"},{"key":"e_1_2_2_33_1","volume-title":"Proceedings of the 13th Annual IEEE\/ACM International Symposium on Code Generation and Optimization (CGO \u201915)","author":"Porpodas Vasileios"},{"key":"e_1_2_2_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1379022.1375609"},{"key":"e_1_2_2_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1133981.1133996"},{"key":"e_1_2_2_36_1","unstructured":"Jaewook Shin Jacqueline Chame and Mary W. Hall. 2003. Exploiting superword-level locality in multimedia extension architectures. Vol. 5.  Jaewook Shin Jacqueline Chame and Mary W. Hall. 2003. Exploiting superword-level locality in multimedia extension architectures. Vol. 5."},{"key":"e_1_2_2_37_1","volume-title":"Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT \u201902)","author":"Shin Jaewook"},{"key":"e_1_2_2_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2005.33"},{"key":"e_1_2_2_39_1","volume-title":"SPEC CP U2017 Benchmark Suite. https:\/\/www.spec.org\/cpu2017\/","author":"Corporation SPEC.","year":"2017"},{"key":"e_1_2_2_40_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1007559022013"},{"key":"e_1_2_2_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.18"},{"key":"e_1_2_2_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2854038.2854054"}],"container-title":["Proceedings of the ACM on Programming Languages"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3276480","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3276480","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3276480","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:01:58Z","timestamp":1750208518000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3276480"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10,24]]},"references-count":42,"journal-issue":{"issue":"OOPSLA","published-print":{"date-parts":[[2018,10,24]]}},"alternative-id":["10.1145\/3276480"],"URL":"https:\/\/doi.org\/10.1145\/3276480","relation":{},"ISSN":["2475-1421"],"issn-type":[{"value":"2475-1421","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,10,24]]},"assertion":[{"value":"2018-10-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}