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Such applications require a large number of address generation instructions and a high degree of memory-level parallelism. This article proposes new memory instructions that exploit strided and indirect memory request patterns and improve efficiency in GPU architectures. The new instructions reduce address calculation instructions by offloading addressing to dedicated hardware, and reduce destructive memory request interference by grouping related requests together. Our results show that we can eliminate\u00a033% of dynamic instructions across 16 GPU benchmarks. These improvements result in an overall runtime improvement of\u00a026%, an energy reduction of\u00a018%, and a reduction in energy-delay product of\u00a032%.<\/jats:p>","DOI":"10.1145\/3280851","type":"journal-article","created":{"date-parts":[[2018,10,29]],"date-time":"2018-10-29T08:02:18Z","timestamp":1540800138000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs"],"prefix":"10.1145","volume":"15","author":[{"given":"Neal C.","family":"Crago","sequence":"first","affiliation":[{"name":"NVIDIA, Santa Clara, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mark","family":"Stephenson","sequence":"additional","affiliation":[{"name":"NVIDIA, Santa Clara, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Stephen W.","family":"Keckler","sequence":"additional","affiliation":[{"name":"NVIDIA, Santa Clara, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2018,10,29]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Retrieved","author":"AMD.","year":"2016","unstructured":"AMD. 2016 . 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