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Storage"],"published-print":{"date-parts":[[2018,11,30]]},"abstract":"<jats:p>\n            We present a framework called Hierarchically Interacting Logs (HIL) for constructing Flash Translation Layers (FTLs). The main goal of the HIL framework is to\n            <jats:italic>heal<\/jats:italic>\n            the Achilles\n            <jats:italic>heel<\/jats:italic>\n            \u2014the crash recovery\u2014of FTLs (hence, its name). Nonetheless, the framework itself is general enough to encompass not only block-mapped and page-mapped FTLs but also many of their variants, including hybrid ones, because of its compositional nature.\n          <\/jats:p>\n          <jats:p>Crash recovery within the HIL framework proceeds in two phases: structural recovery and functional recovery. During the structural recovery, residual effects due to program operations ongoing at the time of the crash are eliminated in an atomic manner using shadow paging. During the functional recovery, operations that would have been performed if there had been no crash are replayed in a redo-only fashion. Both phases operate in an idempotent manner, preventing repeated crashes during recovery from causing any additional problems.<\/jats:p>\n          <jats:p>We demonstrate the practicality of the proposed HIL framework by implementing a prototype and showing that its performance during normal execution and also during crash recovery is at least as good as those of state-of-the-art SSDs.<\/jats:p>","DOI":"10.1145\/3281030","type":"journal-article","created":{"date-parts":[[2018,12,4]],"date-time":"2018-12-04T15:32:40Z","timestamp":1543937560000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["HIL"],"prefix":"10.1145","volume":"14","author":[{"given":"Jin-Yong","family":"Choi","sequence":"first","affiliation":[{"name":"FADU Inc., Korea, Seoul, Korea"}]},{"given":"Eyee Hyun","family":"Nam","sequence":"additional","affiliation":[{"name":"FADU Inc., Korea, Seoul, Korea"}]},{"given":"Yoon Jae","family":"Seong","sequence":"additional","affiliation":[{"name":"FADU Inc., Korea, Seoul, Korea"}]},{"given":"Jin Hyuk","family":"Yoon","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9499-3802","authenticated-orcid":false,"given":"Sookwan","family":"Lee","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, Korea"}]},{"given":"Hong Seok","family":"Kim","sequence":"additional","affiliation":[{"name":"FADU Inc., Korea, Seoul, Korea"}]},{"given":"Jeongsu","family":"Park","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, Korea"}]},{"given":"Yeong-Jae","family":"Woo","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, Korea"}]},{"given":"Sheayun","family":"Lee","sequence":"additional","affiliation":[{"name":"Kookmin University, Seoul, Korea"}]},{"given":"Sang Lyul","family":"Min","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, Korea"}]}],"member":"320","published-online":{"date-parts":[[2018,12,4]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/1404014.1404019"},{"volume-title":"NAND Flash Memory Technologies","author":"Aritome Seiichi","key":"e_1_2_1_2_1","doi-asserted-by":"crossref","DOI":"10.1002\/9781119132639"},{"volume-title":"Arpaci-Dusseau","year":"2015","author":"Arpaci-Dusseau Remzi H.","key":"e_1_2_1_3_1"},{"volume-title":"Concurrency Control and Recovery in Database Systems","author":"Bernstein Philip A.","key":"e_1_2_1_4_1"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1243418.1243429"},{"volume-title":"Proceedings of the 23rd IEEE International Symposium on High Performance Computer Architecture (HPCA\u201917)","author":"Cai Yu","key":"e_1_2_1_7_1"},{"volume-title":"Proceedings of the 8th IEEE International Memory Workshop (IMW\u201916)","author":"Chang Yu-Ming","key":"e_1_2_1_8_1"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0164-1212(99)00059-X"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2915219"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1089733.1089735"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/350853.350863"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/356842.356847"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/2208461.2208463"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508271"},{"volume-title":"Proceedings of the USENIX","year":"1994","author":"Hitz Dave","key":"e_1_2_1_16_1"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2505013"},{"volume-title":"Intel Solid-State Drive DC P3608 Series Product Specification","author":"Intel Corporation 2015.","key":"e_1_2_1_18_1"},{"key":"e_1_2_1_19_1","unstructured":"Intel Corporation and Seagate Technology. 2003. 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