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Code Optim."],"published-print":{"date-parts":[[2018,12,31]]},"abstract":"<jats:p>\n            The marketplace for general-purpose microprocessors offers hundreds of functionally similar models, differing by traits like frequency, core count, cache size, memory bandwidth, and power consumption. Their performance depends not only on microarchitecture, but also on the nature of the workloads being executed. Given a set of intended workloads, the consumer needs both performance and price information to make rational buying decisions. Many benchmark suites have been developed to measure processor performance, and their results for large collections of CPUs are often publicly available. However, repositories of benchmark results are not always helpful when consumers need performance data for\n            <jats:italic>new processors<\/jats:italic>\n            or\n            <jats:italic>new workloads<\/jats:italic>\n            . Moreover, the aggregate scores for benchmark suites designed to cover a broad spectrum of workload types can be misleading. To address these problems, we have developed a deep neural network (DNN) model, and we have used it to learn the relationship between the specifications of Intel CPUs and their performance on the SPEC CPU2006 and Geekbench 3 benchmark suites. We show that we can generate useful predictions for\n            <jats:italic>new processors<\/jats:italic>\n            and\n            <jats:italic>new workloads<\/jats:italic>\n            . We also cross-predict the two benchmark suites and compare their performance scores. The results quantify the self-similarity of these suites for the first time in the literature. This work should discourage consumers from basing purchasing decisions exclusively on Geekbench 3, and it should encourage academics to evaluate research using more diverse workloads than the SPEC CPU suites alone.\n          <\/jats:p>","DOI":"10.1145\/3284127","type":"journal-article","created":{"date-parts":[[2019,1,8]],"date-time":"2019-01-08T15:53:12Z","timestamp":1546962792000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["Predicting New Workload or CPU Performance by Analyzing Public Datasets"],"prefix":"10.1145","volume":"15","author":[{"given":"Yu","family":"Wang","sequence":"first","affiliation":[{"name":"Harvard University, Cambridge, MA, US"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Victor","family":"Lee","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, US"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gu-Yeon","family":"Wei","sequence":"additional","affiliation":[{"name":"Harvard University, Cambridge, MA, US"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"David","family":"Brooks","sequence":"additional","affiliation":[{"name":"Harvard University, Cambridge, MA, US"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,1,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830780"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665705"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2019608.2019609"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2004.1379938"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF02551274"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451125"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541941"},{"key":"e_1_2_1_8_1","volume-title":"Berrar","author":"Dubitzky Werner","year":"2007","unstructured":"Werner Dubitzky , Martin Granzow , and Daniel P . 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The optimum pipeline depth for a microprocessor. In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA\u201902). IEEE Computer Society, 7--13."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1254882.1254937"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152174"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1007\/11549468_24"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168882"},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the 31st Annual International Symposium on Computer Architecture","author":"Tejas","year":"2004","unstructured":"Tejas S. Karkhanis and James E. Smith. 2004. A first-order superscalar processor model . In Proceedings of the 31st Annual International Symposium on Computer Architecture , 2004 . IEEE, 338--349. Tejas S. Karkhanis and James E. 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