{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,29]],"date-time":"2025-11-29T07:54:48Z","timestamp":1764402888077,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,1,21]],"date-time":"2019-01-21T00:00:00Z","timestamp":1548028800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,1,21]]},"DOI":"10.1145\/3287624.3287681","type":"proceedings-article","created":{"date-parts":[[2019,1,18]],"date-time":"2019-01-18T21:45:18Z","timestamp":1547847918000},"page":"761-766","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew"],"prefix":"10.1145","author":[{"given":"Necati","family":"Uysal","sequence":"first","affiliation":[{"name":"University of Central Florida"}]},{"given":"Wen-Hao","family":"Liu","sequence":"additional","affiliation":[{"name":"Cadence Design Systems Inc"}]},{"given":"Rickard","family":"Ewetz","sequence":"additional","affiliation":[{"name":"University of Central Florida"}]}],"member":"320","published-online":{"date-parts":[[2019,1,21]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0166-218X(01)00339-0"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Krit Athikulwongse Xin Zhao and Sung Kyu Lim. 2010. Buffered Clock Tree Sizing for Skew Minimization Under Power and Thermal Budgets (ASP-DAC'10). 474--479.   Krit Athikulwongse Xin Zhao and Sung Kyu Lim. 2010. Buffered Clock Tree Sizing for Skew Minimization Under Power and Thermal Budgets (ASP-DAC'10). 474--479.","DOI":"10.1109\/ASPDAC.2010.5419835"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062184"},{"key":"e_1_3_2_1_4_1","volume-title":"Scalable Construction of Clock Trees with Useful Skew and High Timing Quality. TCAD","author":"Ewetz Rickard","year":"2018","unstructured":"Rickard Ewetz and Cheng-Kok Koh . 2018. Scalable Construction of Clock Trees with Useful Skew and High Timing Quality. TCAD ( 2018 ). Rickard Ewetz and Cheng-Kok Koh. 2018. Scalable Construction of Clock Trees with Useful Skew and High Timing Quality. TCAD (2018)."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.55696"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147171"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"S. Held et al. 2003. Clock scheduling and clocktree construction for high performance ASICs (ICCAD'03). 232--239.   S. Held et al. 2003. Clock scheduling and clocktree construction for high performance ASICs (ICCAD'03). 232--239.","DOI":"10.1109\/ICCAD.2003.159695"},{"key":"e_1_3_2_1_8_1","volume-title":"Markov","author":"Lee Dong-Jin","year":"2011","unstructured":"Dong-Jin Lee and Igor L . Markov . 2011 . Multilevel tree fusion for robust clock networks (ICCAD '2011). 632--639. Dong-Jin Lee and Igor L. Markov. 2011. Multilevel tree fusion for robust clock networks (ICCAD'2011). 632--639."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.494206"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451916.2451956"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160943"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"Subhendu Roy et al. 2015. Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. TCAD (2015) 589--602.  Subhendu Roy et al. 2015. Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. TCAD (2015) 589--602.","DOI":"10.1109\/TCAD.2015.2394310"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1735023.1735058"},{"key":"e_1_3_2_1_14_1","first-page":"1498","article-title":"Dual-V<sub>dd<\/sub> Buffer Insertion for Power Reduction","volume":"27","author":"Tam King Ho","year":"2008","unstructured":"King Ho Tam 2008 . Dual-V<sub>dd<\/sub> Buffer Insertion for Power Reduction . TCAD 27 (2008), 1498 -- 1502 . King Ho Tam et al. 2008. Dual-V<sub>dd<\/sub> Buffer Insertion for Power Reduction. TCAD 27 (2008), 1498--1502.","journal-title":"TCAD"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825875"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","unstructured":"Necati Uysal and Rickard Ewetz. 2018. OCV Guided Clock Tree Topology Reconstruction. In ASP-DAC'18. 1--6.   Necati Uysal and Rickard Ewetz. 2018. OCV Guided Clock Tree Topology Reconstruction. In ASP-DAC'18. 1--6.","DOI":"10.1109\/ASPDAC.2018.8297372"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112223"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996614"}],"event":{"name":"ASPDAC '19: 24th Asia and South Pacific Design Automation Conference","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEICE ESS Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society","IEEE CAS","IEEE CEDA","IPSJ SIG-SLDM Information Processing Society of Japan, SIG System LSI Design Methodology"],"location":"Tokyo Japan","acronym":"ASPDAC '19"},"container-title":["Proceedings of the 24th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3287624.3287681","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3287624.3287681","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:08:05Z","timestamp":1750208885000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3287624.3287681"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,1,21]]},"references-count":18,"alternative-id":["10.1145\/3287624.3287681","10.1145\/3287624"],"URL":"https:\/\/doi.org\/10.1145\/3287624.3287681","relation":{},"subject":[],"published":{"date-parts":[[2019,1,21]]},"assertion":[{"value":"2019-01-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}