{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:32:19Z","timestamp":1750221139508,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,1,21]],"date-time":"2019-01-21T00:00:00Z","timestamp":1548028800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Defense Advanced Research Projects Agency of the USA (DARPA-AFRL)","award":["FA8650-18-1-7819"],"award-info":[{"award-number":["FA8650-18-1-7819"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,1,21]]},"DOI":"10.1145\/3287624.3287683","type":"proceedings-article","created":{"date-parts":[[2019,1,18]],"date-time":"2019-01-18T21:45:18Z","timestamp":1547847918000},"page":"152-159","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["IR-ATA"],"prefix":"10.1145","author":[{"given":"Ashkan","family":"Vakil","sequence":"first","affiliation":[{"name":"George Mason University"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[{"name":"George Mason University"}]},{"given":"Avesta","family":"Sasan","sequence":"additional","affiliation":[{"name":"George Mason University"}]}],"member":"320","published-online":{"date-parts":[[2019,1,21]]},"reference":[{"volume-title":"International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)","author":"Ahmadi R.","key":"e_1_3_2_1_1_1","unstructured":"R. Ahmadi and F. N. Najm . 2003. Timing analysis in presence of power supply and ground voltage variations. In ICCAD-2003 . International Conference on Computer Aided Design (IEEE Cat. No.03CH37486) . 176--183. R. Ahmadi and F. N. Najm. 2003. Timing analysis in presence of power supply and ground voltage variations. In ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486). 176--183."},{"key":"e_1_3_2_1_2_1","volume-title":"https:\/\/www.apache-da.com\/products\/redhawk {Online","author":"Apache ANSYS","year":"2018","unstructured":"ANSYS Apache . 2018. Redhawk. ( 2018 ). https:\/\/www.apache-da.com\/products\/redhawk {Online ; accessed April 17, 2018}. ANSYS Apache. 2018. Redhawk. (2018). https:\/\/www.apache-da.com\/products\/redhawk {Online; accessed April 17, 2018}."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.79"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378489"},{"volume-title":"Signal and Power Integrity - Simplified (3 ed.)","author":"Bogatin Eric","key":"e_1_3_2_1_5_1","unstructured":"Eric Bogatin . 2018. Signal and Power Integrity - Simplified (3 ed.) . Prentice Hall . Eric Bogatin. 2018. Signal and Power Integrity - Simplified (3 ed.). Prentice Hall."},{"volume-title":"https:\/\/www.cadence.com\/content\/cadence-www\/global\/en_US\/home\/tools\/digital-design-and-signoff\/silicon-signoff\/voltus-ic-power-integrity-solution.html {Online","year":"2018","key":"e_1_3_2_1_6_1","unstructured":"Cadence. 2018. Voltus. ( 2018 ). https:\/\/www.cadence.com\/content\/cadence-www\/global\/en_US\/home\/tools\/digital-design-and-signoff\/silicon-signoff\/voltus-ic-power-integrity-solution.html {Online ; accessed June 17, 2018}. Cadence. 2018. Voltus. (2018). https:\/\/www.cadence.com\/content\/cadence-www\/global\/en_US\/home\/tools\/digital-design-and-signoff\/silicon-signoff\/voltus-ic-power-integrity-solution.html {Online; accessed June 17, 2018}."},{"volume-title":"2017 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED). 1--6.","author":"Gunna B.","key":"e_1_3_2_1_7_1","unstructured":"B. Gunna , L. Bhamidipati , H. Homayoun , and A. Sasan . 2017. Spatial and temporal scheduling of clock arrival times for IR hot-spot mitigation, reformulation of peak current reduction . In 2017 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED). 1--6. B. Gunna, L. Bhamidipati, H. Homayoun, and A. Sasan. 2017. Spatial and temporal scheduling of clock arrival times for IR hot-spot mitigation, reformulation of peak current reduction. In 2017 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED). 1--6."},{"key":"e_1_3_2_1_8_1","volume-title":"Kris Gaj, Houman Homayoun, and Avesta Sasan.","author":"Kamali Hadi Mardani","year":"2018","unstructured":"Hadi Mardani Kamali , Kimia Zamiri Azar , Kris Gaj, Houman Homayoun, and Avesta Sasan. 2018 . LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection . arXiv preprint arXiv:1804.11275 (2018). Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, and Avesta Sasan. 2018. LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection. arXiv preprint arXiv:1804.11275 (2018)."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228572"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996745"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.802271"},{"key":"e_1_3_2_1_12_1","volume-title":"IEEE\/ACM International Conference on Computer Aided Design. ICCAD -","author":"Liou Jing-Jia","year":"2000","unstructured":"Jing-Jia Liou , A. Krstic , Yi-Min Jiang , and Kwang-Ting Cheng . 2000 . Path selection and pattern generation for dynamic timing analysis considering power supply noise effects . In IEEE\/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE\/ACM Digest of Technical Papers (Cat. No.00CH37140). 493--496. Jing-Jia Liou, A. Krstic, Yi-Min Jiang, and Kwang-Ting Cheng. 2000. Path selection and pattern generation for dynamic timing analysis considering power supply noise effects. In IEEE\/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE\/ACM Digest of Technical Papers (Cat. No.00CH37140). 493--496."},{"key":"e_1_3_2_1_13_1","volume-title":"IWLS 2005 Benchmarks. (2005","author":"IWLS","year":"2005","unstructured":"IWLS org. 2005 . IWLS 2005 Benchmarks. (2005 ). http:\/\/iwls.org\/iwls2005\/benchmarks.html {Online; accessed April 17, 2018}. IWLS org. 2005. IWLS 2005 Benchmarks. (2005). http:\/\/iwls.org\/iwls2005\/benchmarks.html {Online; accessed April 17, 2018}."},{"key":"e_1_3_2_1_14_1","volume-title":"IEEE\/ACM International Conference on Computer-Aided Design","author":"Pant S.","year":"2005","unstructured":"S. Pant and D. Blaauw . 2005. Static timing analysis considering power supply variations. In ICCAD-2005 . IEEE\/ACM International Conference on Computer-Aided Design , 2005 . 365--371. S. Pant and D. Blaauw. 2005. Static timing analysis considering power supply variations. In ICCAD-2005. IEEE\/ACM International Conference on Computer-Aided Design, 2005. 365--371."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775860"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194596"},{"volume-title":"Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes. In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 275--280","author":"Roshanisefat S.","key":"e_1_3_2_1_17_1","unstructured":"S. Roshanisefat , H. K. Thirumala , K. Gaj , H. Homayoun , and A. Sasan . 2018 . Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes. In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 275--280 . S. Roshanisefat, H. K. Thirumala, K. Gaj, H. Homayoun, and A. Sasan. 2018. Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes. In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 275--280."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.52187"},{"volume-title":"Compsite Current Source Delay Modeling. (2018). synopsys.com\/community\/interoperability\/documents\/interop_dac\/2005_breakfast\/dac05_interop_ccs_synopsys {Online","year":"2018","key":"e_1_3_2_1_19_1","unstructured":"Synopsys. 2018. Compsite Current Source Delay Modeling. (2018). synopsys.com\/community\/interoperability\/documents\/interop_dac\/2005_breakfast\/dac05_interop_ccs_synopsys {Online ; accessed April 17, 2018 }. Synopsys. 2018. Compsite Current Source Delay Modeling. (2018). synopsys.com\/community\/interoperability\/documents\/interop_dac\/2005_breakfast\/dac05_interop_ccs_synopsys {Online; accessed April 17, 2018}."},{"volume-title":"synopsys.com\/implementation-and-signoff\/signoff\/primetime.html {Online","year":"2018","key":"e_1_3_2_1_20_1","unstructured":"Synopsys. 2018. Primetime. ( 2018 ). synopsys.com\/implementation-and-signoff\/signoff\/primetime.html {Online ; accessed April 17, 2018}. Synopsys. 2018. Primetime. (2018). synopsys.com\/implementation-and-signoff\/signoff\/primetime.html {Online; accessed April 17, 2018}."},{"volume-title":"Proceedings of the 1996 Int. Symp. on Low power electronics and design. IEEE Press, 265--270","author":"Vuillod P.","key":"e_1_3_2_1_21_1","unstructured":"P. Vuillod , L. Benini , A. Bogliolo , and G. De Micheli . 1996. Clock skew optimization for peak current reduction . In Proceedings of the 1996 Int. Symp. on Low power electronics and design. IEEE Press, 265--270 . P. Vuillod, L. Benini, A. Bogliolo, and G. De Micheli. 1996. Clock skew optimization for peak current reduction. In Proceedings of the 1996 Int. Symp. on Low power electronics and design. IEEE Press, 265--270."}],"event":{"name":"ASPDAC '19: 24th Asia and South Pacific Design Automation Conference","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEICE ESS Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society","IEEE CAS","IEEE CEDA","IPSJ SIG-SLDM Information Processing Society of Japan, SIG System LSI Design Methodology"],"location":"Tokyo Japan","acronym":"ASPDAC '19"},"container-title":["Proceedings of the 24th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3287624.3287683","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3287624.3287683","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:08:05Z","timestamp":1750208885000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3287624.3287683"}},"subtitle":["IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis &amp; timing closure"],"short-title":[],"issued":{"date-parts":[[2019,1,21]]},"references-count":21,"alternative-id":["10.1145\/3287624.3287683","10.1145\/3287624"],"URL":"https:\/\/doi.org\/10.1145\/3287624.3287683","relation":{},"subject":[],"published":{"date-parts":[[2019,1,21]]},"assertion":[{"value":"2019-01-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}