{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T16:57:12Z","timestamp":1771520232884,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,1,21]],"date-time":"2019-01-21T00:00:00Z","timestamp":1548028800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/100010663","name":"H2020 European Research Council","doi-asserted-by":"publisher","award":["695022"],"award-info":[{"award-number":["695022"]}],"id":[{"id":"10.13039\/100010663","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-1563829"],"award-info":[{"award-number":["CNS-1563829"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,1,21]]},"DOI":"10.1145\/3287624.3288742","type":"proceedings-article","created":{"date-parts":[[2019,1,18]],"date-time":"2019-01-18T21:45:18Z","timestamp":1547847918000},"page":"112-119","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":31,"title":["Insights into the mind of a trojan designer"],"prefix":"10.1145","author":[{"given":"Maik","family":"Ender","sequence":"first","affiliation":[{"name":"Ruhr-Universit\u00e4t Bochum, Bochum, Germany"}]},{"given":"Pawel","family":"Swierczynski","sequence":"additional","affiliation":[{"name":"ESMT, Berlin, Germany"}]},{"given":"Sebastian","family":"Wallat","sequence":"additional","affiliation":[{"name":"University of Massachusetts"}]},{"given":"Matthias","family":"Wilhelm","sequence":"additional","affiliation":[{"name":"Ruhr-Universit\u00e4t Bochum, Bochum, Germany"}]},{"given":"Paul Martin","family":"Knopp","sequence":"additional","affiliation":[{"name":"Ruhr-Universit\u00e4t Bochum, Bochum, Germany"}]},{"given":"Christof","family":"Paar","sequence":"additional","affiliation":[{"name":"Ruhr-Universit\u00e4t Bochum, Bochum, Germany"}]}],"member":"320","published-online":{"date-parts":[[2019,1,21]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"AES T-Box tampering attack. Journal of Cryptographic Engineering","author":"Aldaya A. C.","year":"2015","unstructured":"A. C. Aldaya , A. J. C. Sarmiento , S. S\u00e1nchez-Solano . 2015. AES T-Box tampering attack. Journal of Cryptographic Engineering ( 2015 ), 1--18. A. C. Aldaya, A. J. C. Sarmiento, S. S\u00e1nchez-Solano. 2015. AES T-Box tampering attack. Journal of Cryptographic Engineering (2015), 1--18."},{"key":"e_1_3_2_1_2_1","volume-title":"ALTERA Annual Report for Form 10-K for","year":"2014","unstructured":"Altera. 2015. ALTERA Annual Report for Form 10-K for 2014 . https:\/\/www.sec.gov\/Archives\/edgar\/data\/768251\/000076825115000008\/altera10k12312014.htm. Altera. 2015. ALTERA Annual Report for Form 10-K for 2014. https:\/\/www.sec.gov\/Archives\/edgar\/data\/768251\/000076825115000008\/altera10k12312014.htm."},{"key":"e_1_3_2_1_3_1","volume-title":"BIL: A tool-chain for bitstream reverse-engineering. In Field Programmable Logic and Applications (FPL)","author":"Benz F.","year":"2012","unstructured":"F. Benz , A. Seffrin , and S.A. Huss . 2012 . BIL: A tool-chain for bitstream reverse-engineering. In Field Programmable Logic and Applications (FPL) . IEEE , 735--738. F. Benz, A. Seffrin, and S.A. Huss. 2012. BIL: A tool-chain for bitstream reverse-engineering. In Field Programmable Logic and Applications (FPL). IEEE, 735--738."},{"key":"e_1_3_2_1_4_1","first-page":"2","article-title":"Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream. Design Test","volume":"30","author":"Chakraborty R.S.","year":"2013","unstructured":"R.S. Chakraborty , I. Saha , A. Palchaudhuri , and G.K. Naik . 2013 . Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream. Design Test , IEEE 30 , 2 (April 2013), 45--54. R.S. Chakraborty, I. Saha, A. Palchaudhuri, and G.K. Naik. 2013. Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream. Design Test, IEEE 30, 2 (April 2013), 45--54.","journal-title":"IEEE"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2012.12.003"},{"key":"e_1_3_2_1_6_1","unstructured":"M. Fyrbiak S. Wallat P. Swierczynski M. Hoffmann S. Hoppach M. Wilhelm T. Weidlich R. Tessier and C. Paar. 2018. HAL- The Missing Piece of the Puzzle for Hardware Reverse Engineering Trojan Detection and Insertion. IEEE Transactions on Dependable and Secure Computing (2018) 1--1.  M. Fyrbiak S. Wallat P. Swierczynski M. Hoffmann S. Hoppach M. Wilhelm T. Weidlich R. Tessier and C. Paar. 2018. HAL- The Missing Piece of the Puzzle for Hardware Reverse Engineering Trojan Detection and Insertion. IEEE Transactions on Dependable and Secure Computing (2018) 1--1."},{"key":"e_1_3_2_1_7_1","volume-title":"CCS","author":"Guccione Steve","year":"2011","unstructured":"Steve Guccione , Delon Levi , and Prasanna Sundararajan . 2011 . JBits: Java based interface for reconfigurable computing . In CCS 2011. ACM. Steve Guccione, Delon Levi, and Prasanna Sundararajan. 2011. JBits: Java based interface for reconfigurable computing. In CCS 2011. ACM."},{"key":"e_1_3_2_1_8_1","volume-title":"Kofuji","author":"Horta Edson L.","year":"2002","unstructured":"Edson L. Horta , John W. Lockwood , and S\u00e9rgio T . Kofuji . 2002 . Using PARBIT to Implement Partial Run-Time Reconfigurable Systems. Springer Berlin Heidelberg , Berlin, Heidelberg, 182--191. Edson L. Horta, John W. Lockwood, and S\u00e9rgio T. Kofuji. 2002. Using PARBIT to Implement Partial Run-Time Reconfigurable Systems. Springer Berlin Heidelberg, Berlin, Heidelberg, 182--191."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681429"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2046707.2046722"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-27954-6_1"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435282"},{"key":"e_1_3_2_1_13_1","volume-title":"Workshop on Constructive Side-Channel Analysis and Secure Design. Springer.","author":"Moradi A.","unstructured":"A. Moradi and T. Schneider . 2016. Improved Side-Channel Analysis Attacks on Xilinx Bitstream Encryption of 5, 6, and 7 Series . In Workshop on Constructive Side-Channel Analysis and Secure Design. Springer. A. Moradi and T. Schneider. 2016. Improved Side-Channel Analysis Attacks on Xilinx Bitstream Encryption of 5, 6, and 7 Series. In Workshop on Constructive Side-Channel Analysis and Secure Design. Springer."},{"key":"e_1_3_2_1_14_1","unstructured":"Jean-Francois Nguyen. 2016. Analysing the Bitstream of Altera's MAX-V CPLDs. https:\/\/lse.epita.fr\/lse-summer-week-2016\/slides\/lse-summer-week-2016-07-maxv_cpld.pdf  Jean-Francois Nguyen. 2016. Analysing the Bitstream of Altera's MAX-V CPLDs. https:\/\/lse.epita.fr\/lse-summer-week-2016\/slides\/lse-summer-week-2016-07-maxv_cpld.pdf"},{"key":"e_1_3_2_1_15_1","unstructured":"Jean-Baptiste Note. 2008. debit. https:\/\/github.com\/djn3m0\/debit\/tree\/master\/altera  Jean-Baptiste Note. 2008. debit. https:\/\/github.com\/djn3m0\/debit\/tree\/master\/altera"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344729"},{"key":"e_1_3_2_1_17_1","volume-title":"Automation Test in Europe Conference Exhibition (DATE)","author":"Pham K. Dang","year":"2017","unstructured":"K. Dang Pham , E. Horta , and D. Koch . 2017. BITMAN: A Tool and API for FPGA Bitstream Manipulations. In Design , Automation Test in Europe Conference Exhibition (DATE) , 2017 . 894--897. K. Dang Pham, E. Horta, and D. Koch. 2017. BITMAN: A Tool and API for FPGA Bitstream Manipulations. In Design, Automation Test in Europe Conference Exhibition (DATE), 2017. 894--897."},{"key":"e_1_3_2_1_18_1","volume-title":"Proceedings 16th International Parallel and Distributed Processing Symposium. 6 pp-.","author":"Raghavan A. K.","unstructured":"A. K. Raghavan and P. Sutton . 2002. JPG - a partial bitstream generation tool to support partial reconfiguration in virtex FPGAs . In Proceedings 16th International Parallel and Distributed Processing Symposium. 6 pp-. A. K. Raghavan and P. Sutton. 2002. JPG - a partial bitstream generation tool to support partial reconfiguration in virtex FPGAs. In Proceedings 16th International Parallel and Distributed Processing Symposium. 6 pp-."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950425"},{"key":"e_1_3_2_1_20_1","article-title":"Bitstream Fault Injections (BiFI) - Automated Fault Attacks against SRAM-based FPGAs","author":"Swierczynski Pawel","year":"2017","unstructured":"Pawel Swierczynski , Georg T. Becker , Amir Moradi , and Christof Paar . 2017 . Bitstream Fault Injections (BiFI) - Automated Fault Attacks against SRAM-based FPGAs . IEEE Trans. Comput. PP, 99 ( January 2017), 1--1. Pawel Swierczynski, Georg T. Becker, Amir Moradi, and Christof Paar. 2017. Bitstream Fault Injections (BiFI) - Automated Fault Attacks against SRAM-based FPGAs. IEEE Trans. Comput. PP, 99 (January 2017), 1--1.","journal-title":"IEEE Trans. Comput. PP, 99"},{"key":"e_1_3_2_1_21_1","article-title":"Interdiction in Practice - Hardware Trojan Against a High-Security USB Flash Drive","author":"Swierczynski Pawel","year":"2016","unstructured":"Pawel Swierczynski , Marc Fyrbiak , Philipp Koppe , Amir Moradi , and Christof Paar . 2016 . Interdiction in Practice - Hardware Trojan Against a High-Security USB Flash Drive . Journal of Cryptographic Engineering ( June 2016), 1--13. Pawel Swierczynski, Marc Fyrbiak, Philipp Koppe, Amir Moradi, and Christof Paar. 2016. Interdiction in Practice - Hardware Trojan Against a High-Security USB Flash Drive. Journal of Cryptographic Engineering (June 2016), 1--13.","journal-title":"Journal of Cryptographic Engineering"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2399455"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2629462"},{"key":"e_1_3_2_1_24_1","unstructured":"SymbiFlow. 2017. Project X-Ray. https:\/\/github.com\/SymbiFlow\/prjxray  SymbiFlow. 2017. Project X-Ray. https:\/\/github.com\/SymbiFlow\/prjxray"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2386883"},{"key":"e_1_3_2_1_26_1","volume-title":"2017 IEEE 2nd International Verification and Security Workshop (IVSW). 95--100","author":"Wallat S.","unstructured":"S. Wallat , M. Fyrbiak , M. Schl\u00f6gel , and C. Paar . 2017. A look at the dark side of hardware reverse engineering - a case study . In 2017 IEEE 2nd International Verification and Security Workshop (IVSW). 95--100 . S. Wallat, M. Fyrbiak, M. Schl\u00f6gel, and C. Paar. 2017. A look at the dark side of hardware reverse engineering - a case study. In 2017 IEEE 2nd International Verification and Security Workshop (IVSW). 95--100."},{"key":"e_1_3_2_1_27_1","unstructured":"Clifford Wolf and Mathias Lasser. {n. d.}. Project IceStorm. http:\/\/www.clifford.at\/icestorm\/.  Clifford Wolf and Mathias Lasser. {n. d.}. Project IceStorm. http:\/\/www.clifford.at\/icestorm\/."},{"key":"e_1_3_2_1_28_1","volume-title":"Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. In Field Programmable Logic and Applications, 2006. FPL '06. International Conference on. 1--6.","author":"Ziener D.","unstructured":"D. Ziener , S. Assmus , and J. Teich . 2006 . Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. In Field Programmable Logic and Applications, 2006. FPL '06. International Conference on. 1--6. D. Ziener, S. Assmus, and J. Teich. 2006. Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. In Field Programmable Logic and Applications, 2006. FPL '06. International Conference on. 1--6."}],"event":{"name":"ASPDAC '19: 24th Asia and South Pacific Design Automation Conference","location":"Tokyo Japan","acronym":"ASPDAC '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEICE ESS Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society","IEEE CAS","IEEE CEDA","IPSJ SIG-SLDM Information Processing Society of Japan, SIG System LSI Design Methodology"]},"container-title":["Proceedings of the 24th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3287624.3288742","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3287624.3288742","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3287624.3288742","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T00:57:54Z","timestamp":1750208274000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3287624.3288742"}},"subtitle":["the challenge to integrate a trojan into the bitstream"],"short-title":[],"issued":{"date-parts":[[2019,1,21]]},"references-count":28,"alternative-id":["10.1145\/3287624.3288742","10.1145\/3287624"],"URL":"https:\/\/doi.org\/10.1145\/3287624.3288742","relation":{},"subject":[],"published":{"date-parts":[[2019,1,21]]},"assertion":[{"value":"2019-01-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}