{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,21]],"date-time":"2026-07-21T14:27:32Z","timestamp":1784644052891,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,1,21]],"date-time":"2019-01-21T00:00:00Z","timestamp":1548028800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,1,21]]},"DOI":"10.1145\/3287624.3288756","type":"proceedings-article","created":{"date-parts":[[2019,1,18]],"date-time":"2019-01-18T21:45:18Z","timestamp":1547847918000},"page":"727-732","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":42,"title":["XPPE"],"prefix":"10.1145","author":[{"given":"Hosein Mohammadi","family":"Makrani","sequence":"first","affiliation":[{"name":"George Mason University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hossein","family":"Sayadi","sequence":"additional","affiliation":[{"name":"George Mason University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tinoosh","family":"Mohsenin","sequence":"additional","affiliation":[{"name":"George Mason University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Setareh","family":"rafatirad","sequence":"additional","affiliation":[{"name":"George Mason University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Avesta","family":"Sasan","sequence":"additional","affiliation":[{"name":"George Mason University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[{"name":"George Mason University"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,1,21]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","unstructured":"Kimia Zamiri Azar etal 2019. SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks. IACR Transactions on Cryptographic Hardware and Embedded Systems (2019).  Kimia Zamiri Azar et al. 2019. SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks. IACR Transactions on Cryptographic Hardware and Embedded Systems (2019).","DOI":"10.46586\/tches.v2019.i1.97-122"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Y. Choi and J. Cong. 2017. HLScope: High-Level Performance Debugging for FPGA Designs. In FCCM.  Y. Choi and J. Cong. 2017. HLScope: High-Level Performance Debugging for FPGA Designs. In FCCM.","DOI":"10.1109\/FCCM.2017.44"},{"key":"e_1_3_2_1_3_1","unstructured":"Young-kyu Choi et al. 2017. HLScope+: Fast and accurate performance estimation for FPGA HLS. In ICCAD.   Young-kyu Choi et al. 2017. HLScope+: Fast and accurate performance estimation for FPGA HLS. In ICCAD."},{"key":"e_1_3_2_1_4_1","unstructured":"Steve and others Dai. 2018. Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. In FCCM.  Steve and others Dai. 2018. Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. In FCCM."},{"key":"e_1_3_2_1_5_1","volume-title":"Minerva: Automated hardware optimization tool. In ReConFig.","author":"Farnoud Farahmand","year":"2017","unstructured":"Farnoud Farahmand et al. 2017 . Minerva: Automated hardware optimization tool. In ReConFig. Farnoud Farahmand et al. 2017. Minerva: Automated hardware optimization tool. In ReConFig."},{"key":"e_1_3_2_1_6_1","volume-title":"Chstone: A benchmark program suite for practical c-based high-level synthesis. In ISCAS.","author":"Yuko Hara","year":"2008","unstructured":"Yuko Hara et al. 2008 . Chstone: A benchmark program suite for practical c-based high-level synthesis. In ISCAS. Yuko Hara et al. 2008. Chstone: A benchmark program suite for practical c-based high-level synthesis. In ISCAS."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000832.2000839"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1462586.1462591"},{"key":"e_1_3_2_1_9_1","volume-title":"International Workshop on FPGAs for Software Programmers","author":"Daniel","year":"2015","unstructured":"Daniel Jim\u00e9nez-Gonz\u00e1lez and et.al. 2015. Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC . International Workshop on FPGAs for Software Programmers ( 2015 ). Daniel Jim\u00e9nez-Gonz\u00e1lez and et.al. 2015. Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC. International Workshop on FPGAs for Software Programmers (2015)."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.20"},{"key":"e_1_3_2_1_11_1","volume-title":"Storage Data: An Effective Solution to Alleviate I\/0 Bottleneck in Data-Intensive Workloads","author":"Makrani Hosein Mohammadi","year":"2018","unstructured":"Hosein Mohammadi Makrani 2018 . Compressive Sensing on Storage Data: An Effective Solution to Alleviate I\/0 Bottleneck in Data-Intensive Workloads . In IEEE ASAP. Hosein Mohammadi Makrani et al. 2018. Compressive Sensing on Storage Data: An Effective Solution to Alleviate I\/0 Bottleneck in Data-Intensive Workloads. In IEEE ASAP."},{"key":"e_1_3_2_1_12_1","unstructured":"Hosein Mohammadi Makrani etal 2018. Energy-aware and Machine Learning-based Resource Provisioning of In-Memory Analytics on Cloud. In SoCC.  Hosein Mohammadi Makrani et al. 2018. Energy-aware and Machine Learning-based Resource Provisioning of In-Memory Analytics on Cloud. In SoCC."},{"key":"e_1_3_2_1_13_1","unstructured":"Hosein Mohammadi Makrani and Houman Homayoun. 2017. MeNa: A memory navigator for modern hardware in a scale-out environment. In IISWC.  Hosein Mohammadi Makrani and Houman Homayoun. 2017. MeNa: A memory navigator for modern hardware in a scale-out environment. In IISWC."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3229631.3229639"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"Katayoun Neshatpour et al. 2018. Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce. In FCCM.  Katayoun Neshatpour et al. 2018. Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce. In FCCM.","DOI":"10.1109\/FCCM.2018.00055"},{"key":"e_1_3_2_1_16_1","volume-title":"Parametrization of algorithms and FPGA accelerators to predict performance. Proc","author":"Steffen Craig P","year":"2007","unstructured":"Craig P Steffen . 2007. Parametrization of algorithms and FPGA accelerators to predict performance. Proc . Reconfigurable System Summer Institute ( 2007 ). Craig P Steffen. 2007. Parametrization of algorithms and FPGA accelerators to predict performance. Proc. Reconfigurable System Summer Institute (2007)."},{"key":"e_1_3_2_1_17_1","volume-title":"Machsuite: Benchmarks for accelerator design and customized architectures. In IISWC.","author":"Brandon Reagen","year":"2014","unstructured":"Brandon Reagen et al. 2014 . Machsuite: Benchmarks for accelerator design and customized architectures. In IISWC. Brandon Reagen et al. 2014. Machsuite: Benchmarks for accelerator design and customized architectures. In IISWC."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"S. Rezaei and et.al. 2016. Data-rate-aware FPGA-based acceleration framework for streaming applications. In ReConFig.  S. Rezaei and et.al. 2016. Data-rate-aware FPGA-based acceleration framework for streaming applications. In ReConFig.","DOI":"10.1109\/ReConFig.2016.7857162"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194596"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"crossref","unstructured":"Hossein Sayadi et al. 2017. Machine learning-based approaches for energy-efficiency prediction and scheduling in composite cores architectures. In ICCD.  Hossein Sayadi et al. 2017. Machine learning-based approaches for energy-efficiency prediction and scheduling in composite cores architectures. In ICCD.","DOI":"10.1109\/ICCD.2017.28"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"crossref","unstructured":"Hossein Sayadi et al. 2018. Customized machine learning-based hardware-assisted malware detection in embedded devices. In TrustCom\/BigDataSE.  Hossein Sayadi et al. 2018. Customized machine learning-based hardware-assisted malware detection in embedded devices. In TrustCom\/BigDataSE.","DOI":"10.1109\/TrustCom\/BigDataSE.2018.00251"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196047"},{"key":"e_1_3_2_1_23_1","unstructured":"Benjamin Carrion Schafer etal 2014. S2CBench: Synthesizable SystemC benchmark suite for high-level synthesis. IEEE Embedded Systems Letters (2014).  Benjamin Carrion Schafer et al. 2014. S2CBench: Synthesizable SystemC benchmark suite for high-level synthesis. IEEE Embedded Systems Letters (2014)."},{"key":"e_1_3_2_1_24_1","volume-title":"Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures. In ISCA.","author":"Shao Y. S.","year":"2014","unstructured":"Y. S. Shao 2014 . Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures. In ISCA. Y. S. Shao et al. 2014. Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures. In ISCA."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"crossref","unstructured":"J. Stangl et al. 2018. A Fast and Resource Efficient FPGA Implementation of Secret Sharing for Storage Applications. In DATE.  J. Stangl et al. 2018. A Fast and Resource Efficient FPGA Implementation of Secret Sharing for Storage Applications. In DATE.","DOI":"10.23919\/DATE.2018.8342091"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287683"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"Guanwen Zhong et al. 2017. Design Space exploration of FPGA-based accelerators with multi-level parallelism. In DATE.   Guanwen Zhong et al. 2017. Design Space exploration of FPGA-based accelerators with multi-level parallelism. In DATE.","DOI":"10.23919\/DATE.2017.7927161"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898040"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174255"}],"event":{"name":"ASPDAC '19: 24th Asia and South Pacific Design Automation Conference","location":"Tokyo Japan","acronym":"ASPDAC '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEICE ESS Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society","IEEE CAS","IEEE CEDA","IPSJ SIG-SLDM Information Processing Society of Japan, SIG System LSI Design Methodology"]},"container-title":["Proceedings of the 24th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3287624.3288756","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3287624.3288756","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T00:57:54Z","timestamp":1750208274000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3287624.3288756"}},"subtitle":["cross-platform performance estimation of hardware accelerators using machine learning"],"short-title":[],"issued":{"date-parts":[[2019,1,21]]},"references-count":29,"alternative-id":["10.1145\/3287624.3288756","10.1145\/3287624"],"URL":"https:\/\/doi.org\/10.1145\/3287624.3288756","relation":{},"subject":[],"published":{"date-parts":[[2019,1,21]]},"assertion":[{"value":"2019-01-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}