{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:32:10Z","timestamp":1750221130375,"version":"3.41.0"},"reference-count":31,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2019,1,30]],"date-time":"2019-01-30T00:00:00Z","timestamp":1548806400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2019,1,31]]},"abstract":"<jats:p>Fabrication-less integrated circuit (IC) design houses outsource fabrication to third-party foundries to reduce cost of manufacturing. The outsourcing of IC fabrication, beyond our expectation, raises concerns regarding intellectual property (IP) piracy and theft by rogue elements in the third-party foundries. Obfuscation techniques have been proposed to increase resistance to reverse engineering, IP recovery, IP theft, and piracy. However, prior work on obfuscation for IP protection has primarily applied to the gate level or the layout level. As a result, it can significantly impact the performance of the original design in addition to requiring redesign of standard cells.<\/jats:p>\n          <jats:p>In this article, we propose a high-level synthesis and analysis (HLSA)-based obfuscation approach for IP protection. The proposed method is based on split manufacturing. Additional dummy units and MUXes can be added to further obfuscate the design. The proposed technique aligns with the standard-cell-based design methodologies and does not significantly impact the performance of the original design. Our experimental results confirm that the proposed approach can provide high levels of IC obfuscation with moderate area cost.<\/jats:p>","DOI":"10.1145\/3289156","type":"journal-article","created":{"date-parts":[[2019,1,30]],"date-time":"2019-01-30T12:58:34Z","timestamp":1548853114000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Split Manufacturing-Based Register Transfer-Level Obfuscation"],"prefix":"10.1145","volume":"15","author":[{"given":"Xiaotong","family":"Cui","sequence":"first","affiliation":[{"name":"Chongqing University of Posts and Telecommunications, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeff (Jun)","family":"Zhang","sequence":"additional","affiliation":[{"name":"New York University, New York, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaijie","family":"Wu","sequence":"additional","affiliation":[{"name":"New York University, New York, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Siddharth","family":"Garg","sequence":"additional","affiliation":[{"name":"New York University, New York, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramesh","family":"Karri","sequence":"additional","affiliation":[{"name":"New York University, New York, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,1,30]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1007\/s10617-005-1395-x"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the USENIX Security Symposium. 291--306","author":"Alkabani Yousra","year":"2007","unstructured":"Yousra Alkabani and Farinaz Koushanfar . 2007 . Active hardware metering for intellectual property protection and security . In Proceedings of the USENIX Security Symposium. 291--306 . Yousra Alkabani and Farinaz Koushanfar. 2007. Active hardware metering for intellectual property protection and security. In Proceedings of the USENIX Security Symposium. 291--306."},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1109\/MDT.2010.24"},{"doi-asserted-by":"publisher","key":"e_1_2_1_4_1","DOI":"10.1109\/HST.2010.5513117"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1109\/TCAD.2009.2028166"},{"doi-asserted-by":"publisher","key":"e_1_2_1_6_1","DOI":"10.1109\/TCSI.2009.2035415"},{"volume-title":"Secure System Design and Trustable Computing","author":"Chang Chip-Hong","unstructured":"Chip-Hong Chang , Miodrag Potkonjak , and Li Zhang . 2016. Hardware IP watermarking and fingerprinting . In Secure System Design and Trustable Computing . Springer , 329--368. Chip-Hong Chang, Miodrag Potkonjak, and Li Zhang. 2016. Hardware IP watermarking and fingerprinting. In Secure System Design and Trustable Computing. Springer, 329--368.","key":"e_1_2_1_7_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_8_1","DOI":"10.1145\/2593069.2593150"},{"doi-asserted-by":"publisher","key":"e_1_2_1_9_1","DOI":"10.1109\/DFT.2016.7684088"},{"doi-asserted-by":"publisher","key":"e_1_2_1_10_1","DOI":"10.1049\/el:20030874"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the 22nd USENIX Security Symposium (USENIXSecurity\u201913)","author":"Imeson Frank","year":"2013","unstructured":"Frank Imeson , Ariq Emtenan , Siddharth Garg , and Mahesh Tripunitara . 2013 . Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation . In Proceedings of the 22nd USENIX Security Symposium (USENIXSecurity\u201913) . 495--510. Frank Imeson, Ariq Emtenan, Siddharth Garg, and Mahesh Tripunitara. 2013. Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation. In Proceedings of the 22nd USENIX Security Symposium (USENIXSecurity\u201913). 495--510."},{"unstructured":"Commission IP. 2013. The commission report on theft of American intellectual property. Retrieved from http:\/\/www.ipcommission.org\/report\/IP_Commission_Report_052213.pdf.  Commission IP. 2013. The commission report on theft of American intellectual property. Retrieved from http:\/\/www.ipcommission.org\/report\/IP_Commission_Report_052213.pdf.","key":"e_1_2_1_12_1"},{"key":"e_1_2_1_13_1","first-page":"195","article-title":"Advanced Micro Devices Inc","volume":"7","author":"Jarvis Richard Wayne","year":"2007","unstructured":"Richard Wayne Jarvis and Michael G. Mcintyre . 2007 . Advanced Micro Devices Inc . Split Manufacturing Method for Advanced Semiconductor Circuits. U.S. Patent 7 , 195 ,931. Richard Wayne Jarvis and Michael G. Mcintyre. 2007. Advanced Micro Devices Inc. Split Manufacturing Method for Advanced Semiconductor Circuits. U.S. Patent 7,195,931.","journal-title":"Split Manufacturing Method for Advanced Semiconductor Circuits. U.S. Patent"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the 3rd International Conference on Electronics Computer Technology (ICECT\u201911)","volume":"4","author":"Mebin Jose V. I.","unstructured":"V. I. Mebin Jose , W. Newtondavidraj , and P. Daniel . 2011. Watermarking techniques for IP identification based on testing in SOC design at behavioural level . In Proceedings of the 3rd International Conference on Electronics Computer Technology (ICECT\u201911) , Vol. 4 . IEEE, 84--88. V. I. Mebin Jose, W. Newtondavidraj, and P. Daniel. 2011. Watermarking techniques for IP identification based on testing in SOC design at behavioural level. In Proceedings of the 3rd International Conference on Electronics Computer Technology (ICECT\u201911), Vol. 4. IEEE, 84--88."},{"doi-asserted-by":"publisher","key":"e_1_2_1_15_1","DOI":"10.1109\/TIFS.2011.2163307"},{"doi-asserted-by":"publisher","key":"e_1_2_1_16_1","DOI":"10.1109\/TCAD.2006.884574"},{"doi-asserted-by":"publisher","key":"e_1_2_1_17_1","DOI":"10.1145\/309847.310080"},{"doi-asserted-by":"publisher","key":"e_1_2_1_18_1","DOI":"10.1109\/TVLSI.2014.2323976"},{"doi-asserted-by":"publisher","key":"e_1_2_1_19_1","DOI":"10.1109\/EURDAC.1993.410610"},{"doi-asserted-by":"publisher","key":"e_1_2_1_20_1","DOI":"10.1109\/43.945306"},{"unstructured":"Trusted Integrated Circuits Program. {n.d.}. Intelligence advanced research projects activity. Retrieved from https:\/\/www.fbo.gov\/utils\/view?id&equals;b8be3d2c5d5babbdffc6975c370247a6.  Trusted Integrated Circuits Program. {n.d.}. Intelligence advanced research projects activity. Retrieved from https:\/\/www.fbo.gov\/utils\/view?id&equals;b8be3d2c5d5babbdffc6975c370247a6.","key":"e_1_2_1_21_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_22_1","DOI":"10.1109\/TCAD.2015.2428707"},{"doi-asserted-by":"publisher","key":"e_1_2_1_23_1","DOI":"10.5555\/2485288.2485591"},{"doi-asserted-by":"publisher","key":"e_1_2_1_24_1","DOI":"10.1109\/TVLSI.2016.2530092"},{"doi-asserted-by":"publisher","key":"e_1_2_1_25_1","DOI":"10.1109\/MC.2010.284"},{"key":"e_1_2_1_26_1","volume-title":"White Paper 1","author":"Saban Kirk","year":"2011","unstructured":"Kirk Saban . 2011. Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency. Xilinx , White Paper 1 ( 2011 ), wP380. Kirk Saban. 2011. Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency. Xilinx, White Paper 1 (2011), wP380."},{"doi-asserted-by":"publisher","key":"e_1_2_1_27_1","DOI":"10.1109\/ACCESS.2016.2552058"},{"key":"e_1_2_1_28_1","article-title":"CMOS design of area and power efficient multiplexer using tree topology","volume":"112","author":"Thakur Yashika","year":"2015","unstructured":"Yashika Thakur , Rajesh Mehra , and Anjali Sharma . 2015 . CMOS design of area and power efficient multiplexer using tree topology . Int. J. Comput. Appl. 112 , 11 (2015). Yashika Thakur, Rajesh Mehra, and Anjali Sharma. 2015. CMOS design of area and power efficient multiplexer using tree topology. Int. J. Comput. Appl. 112, 11 (2015).","journal-title":"Int. J. Comput. Appl."},{"doi-asserted-by":"publisher","key":"e_1_2_1_29_1","DOI":"10.1109\/TETC.2016.2585046"},{"doi-asserted-by":"publisher","key":"e_1_2_1_30_1","DOI":"10.1145\/2897937.2898104"},{"doi-asserted-by":"publisher","key":"e_1_2_1_31_1","DOI":"10.1109\/HST.2015.7140229"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3289156","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3289156","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:02:23Z","timestamp":1750208543000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3289156"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,1,30]]},"references-count":31,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2019,1,31]]}},"alternative-id":["10.1145\/3289156"],"URL":"https:\/\/doi.org\/10.1145\/3289156","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2019,1,30]]},"assertion":[{"value":"2017-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-01-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}