{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,12]],"date-time":"2026-02-12T13:47:43Z","timestamp":1770904063144,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,2,20]],"date-time":"2019-02-20T00:00:00Z","timestamp":1550620800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["HR0011-12-2-0016"],"award-info":[{"award-number":["HR0011-12-2-0016"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,2,20]]},"DOI":"10.1145\/3289602.3293894","type":"proceedings-article","created":{"date-parts":[[2019,2,22]],"date-time":"2019-02-22T22:12:13Z","timestamp":1550873533000},"page":"330-339","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":27,"title":["FASED"],"prefix":"10.1145","author":[{"given":"David","family":"Biancolin","sequence":"first","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Sagar","family":"Karandikar","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Donggyu","family":"Kim","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Jack","family":"Koenig","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Andrew","family":"Waterman","sequence":"additional","affiliation":[{"name":"SiFive Inc., San Mateo, CA, USA"}]},{"given":"Jonathan","family":"Bachrach","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, Berkeley, CA, USA"}]},{"given":"Krste","family":"Asanovic","sequence":"additional","affiliation":[{"name":"University of California, Berkeley &amp; SiFive Inc., Berkeley, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2019,2,20]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Amazon. 2016. Amazon EC2 F1 Instances (Preview). https:\/\/aws.amazon.com\/ ec2\/instance-types\/f1\/.  Amazon. 2016. Amazon EC2 F1 Instances (Preview). https:\/\/aws.amazon.com\/ ec2\/instance-types\/f1\/."},{"key":"e_1_3_2_1_2_1","volume-title":"Technical Report UCB\/EECS-2016--17. EECS Department","author":"Krste Asanovic","year":"2016","unstructured":"Krste Asanovic et al. 2016 . The Rocket Chip Generator. Technical Report UCB\/EECS-2016--17. EECS Department , University of California, Berkeley . Krste Asanovic et al. 2016. The Rocket Chip Generator. Technical Report UCB\/EECS-2016--17. EECS Department, University of California, Berkeley."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"e_1_3_2_1_4_1","unstructured":"Niladrish Chatterjee et al. 2012. USIMM: the Utah SImulated Memory Module A Simulation Infrastructure for the JWAC Memory Scheduling Championship.  Niladrish Chatterjee et al. 2012. USIMM: the Utah SImulated Memory Module A Simulation Infrastructure for the JWAC Memory Scheduling Championship."},{"key":"e_1_3_2_1_5_1","volume-title":"Cycle-Accurate Simulators. In Proceedings of the 40th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 40)","author":"Derek","unstructured":"Derek Chiou et al. 2007. FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System , Cycle-Accurate Simulators. In Proceedings of the 40th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 40) . IEEE Computer Society, Washington, DC, USA, 249--261. Derek Chiou et al. 2007. FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators. In Proceedings of the 40th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 40). IEEE Computer Society, Washington, DC, USA, 249--261."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344684"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2012.6189225"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145725"},{"key":"e_1_3_2_1_9_1","volume-title":"Proceedings of the 36th International Conference on Computer-Aided Design (ICCAD '17)","author":"Adam","unstructured":"Adam Izraelevitz et al. 2017. Reusability is FIRRTL Ground: Hardware Construction Languages, Compiler Frameworks, and Transformations . In Proceedings of the 36th International Conference on Computer-Aided Design (ICCAD '17) . IEEE Press, Piscataway, NJ, USA, 209--216. Adam Izraelevitz et al. 2017. Reusability is FIRRTL Ground: Hardware Construction Languages, Compiler Frameworks, and Transformations. In Proceedings of the 36th International Conference on Computer-Aided Design (ICCAD '17). IEEE Press, Piscataway, NJ, USA, 209--216."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00014"},{"key":"e_1_3_2_1_11_1","volume-title":"Emulation of Microprocessor Memory Systems Using the RAMP Design Framework. Master's thesis","author":"Asif I.","unstructured":"Asif I. Khan . 2008. Emulation of Microprocessor Memory Systems Using the RAMP Design Framework. Master's thesis . Massachusetts Institute of Technology . Asif I. Khan. 2008. Emulation of Microprocessor Memory Systems Using the RAMP Design Framework. Master's thesis. Massachusetts Institute of Technology."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.21"},{"key":"e_1_3_2_1_13_1","volume-title":"Evaluation of RISC-V RTL with FPGA-Acclerated Simulation. In CARRV '17","author":"Donggyu","unstructured":"Donggyu Kim et al. 2017 . Evaluation of RISC-V RTL with FPGA-Acclerated Simulation. In CARRV '17 . Donggyu Kim et al. 2017. Evaluation of RISC-V RTL with FPGA-Acclerated Simulation. In CARRV '17."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1987.13876"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1575774.1575775"},{"key":"e_1_3_2_1_17_1","volume-title":"Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA '11)","author":"Michael","year":"2014","unstructured":"Michael Pellauer et al. 2011. HAsim: FPGA-based High-detail Multicore Simulation Using Time-division Multiplexing . In Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA '11) . IEEE Computer Society, Washington, DC, USA, 406--417. http:\/\/dl.acm.org\/ citation.cfm?id= 2014 698.2014876 Michael Pellauer et al. 2011. HAsim: FPGA-based High-detail Multicore Simulation Using Time-division Multiplexing. In Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA '11). IEEE Computer Society, Washington, DC, USA, 406--417. http:\/\/dl.acm.org\/ citation.cfm?id=2014698.2014876"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837390"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694362"},{"key":"e_1_3_2_1_22_1","volume-title":"Proceedings of the 7th IEEE\/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE'09)","author":"Muralidaran","unstructured":"Muralidaran Vijayaraghavan et al. 2009. Bounded Dataflow Networks and Latency-insensitive Circuits . In Proceedings of the 7th IEEE\/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE'09) . IEEE Press, Piscataway, NJ, USA, 171--180. http:\/\/dl.acm.org\/citation.cfm?id=1715759. 1715781 Muralidaran Vijayaraghavan et al. 2009. Bounded Dataflow Networks and Latency-insensitive Circuits. In Proceedings of the 7th IEEE\/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE'09). IEEE Press, Piscataway, NJ, USA, 171--180. http:\/\/dl.acm.org\/citation.cfm?id=1715759. 1715781"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.39"},{"key":"e_1_3_2_1_24_1","first-page":"10","article-title":"Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design","volume":"22","author":"Henry Wong","year":"2014","unstructured":"Henry Wong et al. 2014 . Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design . IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 , 10 (Oct 2014), 2067--2080. Henry Wong et al. 2014. Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 10 (Oct 2014), 2067--2080.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"}],"event":{"name":"FPGA '19: The 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","location":"Seaside CA USA","acronym":"FPGA '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3289602.3293894","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3289602.3293894","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3289602.3293894","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:02:22Z","timestamp":1750208542000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3289602.3293894"}},"subtitle":["FPGA-Accelerated Simulation and Evaluation of DRAM"],"short-title":[],"issued":{"date-parts":[[2019,2,20]]},"references-count":24,"alternative-id":["10.1145\/3289602.3293894","10.1145\/3289602"],"URL":"https:\/\/doi.org\/10.1145\/3289602.3293894","relation":{},"subject":[],"published":{"date-parts":[[2019,2,20]]},"assertion":[{"value":"2019-02-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}