{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T01:42:38Z","timestamp":1787017358563,"version":"build-2736575974"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,2,20]],"date-time":"2019-02-20T00:00:00Z","timestamp":1550620800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"NSF\/Intel","award":["1723773"],"award-info":[{"award-number":["1723773"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,2,20]]},"DOI":"10.1145\/3289602.3293918","type":"proceedings-article","created":{"date-parts":[[2019,2,22]],"date-time":"2019-02-22T17:12:13Z","timestamp":1550855533000},"page":"178-183","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["Rapid Cycle-Accurate Simulator for High-Level Synthesis"],"prefix":"10.1145","author":[{"given":"Yuze","family":"Chi","sequence":"first","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Young-kyu","family":"Choi","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jason","family":"Cong","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jie","family":"Wang","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,2,20]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"AlphaData. 2017. Alpha Data ADM-PCIE-KU3 Datasheet. (2017). http:\/\/www. alpha-data.com\/pdfs\/adm-pcie-ku3.pdf  AlphaData. 2017. Alpha Data ADM-PCIE-KU3 Datasheet. (2017). http:\/\/www. alpha-data.com\/pdfs\/adm-pcie-ku3.pdf"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/2555729.2555747"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240850"},{"key":"e_1_3_2_1_4_1","volume-title":"IEEE Ann. Int. Symp. Field-Programmable Custom Computing Machines (FCCM'17)","author":"Choi Y.","unstructured":"Y. Choi and J. Cong . 2017. HLScope: High-level performance debugging for FPGA designs ,. In IEEE Ann. Int. Symp. Field-Programmable Custom Computing Machines (FCCM'17) . 125--128. Y. Choi and J. Cong. 2017. HLScope: High-level performance debugging for FPGA designs,. In IEEE Ann. Int. Symp. Field-Programmable Custom Computing Machines (FCCM'17). 125--128."},{"key":"e_1_3_2_1_5_1","volume-title":"Proc. IEEE\/ACM Int. Conf. Computer-Aided Design (ICCAD'17)","author":"Choi Y.","unstructured":"Y. Choi , P. Zhang , P. Li , and J. Cong . 2017. HLScope+: Fast and accurate performance estimation for FPGA HLS . In Proc. IEEE\/ACM Int. Conf. Computer-Aided Design (ICCAD'17) . 691--698. Y. Choi, P. Zhang, P. Li, and J. Cong. 2017. HLScope+: Fast and accurate performance estimation for FPGA HLS. In Proc. IEEE\/ACM Int. Conf. Computer-Aided Design (ICCAD'17). 691--698."},{"key":"e_1_3_2_1_6_1","volume-title":"IEEE Int. Symp. Circuits and Systems (ISCAS'14)","author":"Chung M.","unstructured":"M. Chung , J. Kim , and S. Ryu . 2014. SimParallel: A high performance parallel SystemC simulator using hierarchical multi-threading . In IEEE Int. Symp. Circuits and Systems (ISCAS'14) . 1472--1475. M. Chung, J. Kim, and S. Ryu. 2014. SimParallel: A high performance parallel SystemC simulator using hierarchical multi-threading. In IEEE Int. Symp. Circuits and Systems (ISCAS'14). 1472--1475."},{"key":"e_1_3_2_1_7_1","unstructured":"J. Cong Z. Fang H. Kianinejad and P. Wei. 2016. Revisiting FPGA acceleration of molecular dynamics simulation with dynamic data flow behavior in high-level synthesis. ArXiv Preprint (2016). http:\/\/https:\/\/arxiv.org\/pdf\/1611.04474.pdf  J. Cong Z. Fang H. Kianinejad and P. Wei. 2016. Revisiting FPGA acceleration of molecular dynamics simulation with dynamic data flow behavior in high-level synthesis. ArXiv Preprint (2016). http:\/\/https:\/\/arxiv.org\/pdf\/1611.04474.pdf"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240838"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.69"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593143"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.25"},{"key":"e_1_3_2_1_13_1","unstructured":"Intel. 2018. Intel Xeon Processor E5--2680 v4. (2018). www.intel.com\/  Intel. 2018. Intel Xeon Processor E5--2680 v4. (2018). www.intel.com\/"},{"key":"e_1_3_2_1_14_1","unstructured":"Intel. 2018. Intel FPGA SDK for OpenCL Pro Edition. (2018). https:\/\/www.altera. com\/en_US\/pdfs\/literature\/hb\/opencl-sdk\/aocl-best-practices-guide.pdf  Intel. 2018. Intel FPGA SDK for OpenCL Pro Edition. (2018). https:\/\/www.altera. com\/en_US\/pdfs\/literature\/hb\/opencl-sdk\/aocl-best-practices-guide.pdf"},{"key":"e_1_3_2_1_15_1","unstructured":"Intel. 2018. Quartus Prime Pro Edition Handbook. (2018). www.intel.com\/  Intel. 2018. Quartus Prime Pro Edition Handbook. (2018). www.intel.com\/"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859562"},{"key":"e_1_3_2_1_17_1","unstructured":"S. Lahti P. Sj\u00f6vall and J. Vanne. 2018. Are we there yet? A study on the state of high-level synthesis. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (2018).  S. Lahti P. Sj\u00f6vall and J. Vanne. 2018. Are we there yet? A study on the state of high-level synthesis. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (2018)."},{"key":"e_1_3_2_1_18_1","volume-title":"IEEE Int. Conf. Field Programmable Logic and Appl. (FPL'14)","author":"Monson J.","unstructured":"J. Monson and B. Hutchings . 2014. New approaches for in-system debug of behaviorally-synthesized FPGA circuits ,. In IEEE Int. Conf. Field Programmable Logic and Appl. (FPL'14) . J. Monson and B. Hutchings. 2014. New approaches for in-system debug of behaviorally-synthesized FPGA circuits,. In IEEE Int. Conf. Field Programmable Logic and Appl. (FPL'14)."},{"key":"e_1_3_2_1_19_1","unstructured":"ROSE. 2018. ROSE compiler infrastructure. (2018). http:\/\/rosecompiler.org\/  ROSE. 2018. ROSE compiler infrastructure. (2018). http:\/\/rosecompiler.org\/"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062243"},{"key":"e_1_3_2_1_21_1","volume-title":"IEEE Int. Conf. Comput. Design (ICCD'17)","author":"Sozzo E.","year":"2017","unstructured":"E. Sozzo , 2017 . A common backend for hardware acceleration on FPGA . In IEEE Int. Conf. Comput. Design (ICCD'17) . 427--430. E. Sozzo, et al. 2017. A common backend for hardware acceleration on FPGA. In IEEE Int. Conf. Comput. Design (ICCD'17). 427--430."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062230"},{"key":"e_1_3_2_1_23_1","unstructured":"Xilinx. 2018. UltraScale architecture and product data sheet: overview (DS890). (2018). https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ ds890-ultrascale-overview.pdf  Xilinx. 2018. UltraScale architecture and product data sheet: overview (DS890). (2018). https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ ds890-ultrascale-overview.pdf"},{"key":"e_1_3_2_1_24_1","unstructured":"Xilinx. 2018. Vivado High-level Synthesis (UG902). (2018). https: \/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2018_2\/ ug902-vivado-high-level-synthesis.pdf  Xilinx. 2018. Vivado High-level Synthesis (UG902). (2018). https: \/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2018_2\/ ug902-vivado-high-level-synthesis.pdf"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196109"}],"event":{"name":"FPGA '19: The 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","location":"Seaside CA USA","acronym":"FPGA '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3289602.3293918","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3289602.3293918","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:02:07Z","timestamp":1750194127000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3289602.3293918"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2,20]]},"references-count":25,"alternative-id":["10.1145\/3289602.3293918","10.1145\/3289602"],"URL":"https:\/\/doi.org\/10.1145\/3289602.3293918","relation":{},"subject":[],"published":{"date-parts":[[2019,2,20]]},"assertion":[{"value":"2019-02-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}