{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:31:58Z","timestamp":1750221118615,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,2,20]],"date-time":"2019-02-20T00:00:00Z","timestamp":1550620800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"NSERC","award":["COHESA"],"award-info":[{"award-number":["COHESA"]}]},{"name":"Intel","award":["FPGA Program-ming Optimizations ISRA"],"award-info":[{"award-number":["FPGA Program-ming Optimizations ISRA"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,2,20]]},"DOI":"10.1145\/3289602.3293922","type":"proceedings-article","created":{"date-parts":[[2019,2,22]],"date-time":"2019-02-22T22:12:13Z","timestamp":1550873533000},"page":"110-115","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["On-chip FPGA Debug Instrumentation for Machine Learning Applications"],"prefix":"10.1145","author":[{"given":"Daniel","family":"Holanda Noronha","sequence":"first","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ruizhe","family":"Zhao","sequence":"additional","affiliation":[{"name":"Imperial College London, London, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeff","family":"Goeders","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Luk","sequence":"additional","affiliation":[{"name":"Imperial College London, London, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J.E.","family":"Wilton","sequence":"additional","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,2,20]]},"reference":[{"volume-title":"Quartus Prime Pro Edition Handbook","key":"e_1_3_2_1_1_1","unstructured":"Altera. 2015. Quartus Prime Pro Edition Handbook . Vol. 3 . Chapter 9: Design Debugging Using the SignalTap II Logic Analyzer. Altera. 2015. Quartus Prime Pro Edition Handbook . Vol. 3. Chapter 9: Design Debugging Using the SignalTap II Logic Analyzer."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"N. Calagar S.D. Brown and J.H. Anderson. 2014. Source-level Debugging for FPGA High-Level Synthesis. In Int'l Conf. on Field Programmable Logic and Applications .  N. Calagar S.D. Brown and J.H. Anderson. 2014. Source-level Debugging for FPGA High-Level Synthesis. In Int'l Conf. on Field Programmable Logic and Applications .","DOI":"10.1109\/FPL.2014.6927496"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","unstructured":"F. Eslami and S. J. E. Wilton. 2015. An adaptive virtual overlay for fast trigger insertion for FPGA debug. In Int'l Conf. on Field Programmable Technology (FPT) .  F. Eslami and S. J. E. Wilton. 2015. An adaptive virtual overlay for fast trigger insertion for FPGA debug. In Int'l Conf. on Field Programmable Technology (FPT) .","DOI":"10.1109\/FPT.2015.7393127"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927498"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2565204"},{"volume-title":"Symposium on Field-Programmable Custom Computing Machines. 228--237","author":"Hemmert K.S.","key":"e_1_3_2_1_6_1","unstructured":"K.S. Hemmert , J.L. Tripp , B.L. Hutchings , and P.A. Jackson . 2003. Source level debugger for the Sea Cucumber synthesizing compiler . In Symposium on Field-Programmable Custom Computing Machines. 228--237 . K.S. Hemmert, J.L. Tripp, B.L. Hutchings, and P.A. Jackson. 2003. Source level debugger for the Sea Cucumber synthesizing compiler. In Symposium on Field-Programmable Custom Computing Machines. 228--237."},{"volume-title":"LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks. In International Workshop on FPGAs for Software Programmers .","author":"Noronha D. Holanda","key":"e_1_3_2_1_7_1","unstructured":"D. Holanda Noronha , B. Salehpour , and S. Wilton . 2018 . LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks. In International Workshop on FPGAs for Software Programmers . D. Holanda Noronha, B. Salehpour, and S. Wilton. 2018. LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks. In International Workshop on FPGAs for Software Programmers ."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2618862"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174254"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3154484"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"A. Kourfali and D. Stroobandt. 2016. Efficient Hardware Debugging using Parameterized FPGA Reconfiguration. In Int'l Parallel and Distributed Processing Symposium Workshop. 277--282.  A. Kourfali and D. Stroobandt. 2016. Efficient Hardware Debugging using Parameterized FPGA Reconfiguration. In Int'l Parallel and Distributed Processing Symposium Workshop. 277--282.","DOI":"10.1109\/IPDPSW.2016.95"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"S.I. Venieris and C. Bouganis. 2016. fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs. In 2016 Int'l Symposium on Field-Programmable Custom Computing Machines (FCCM) . 40--47.  S.I. Venieris and C. Bouganis. 2016. fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs. In 2016 Int'l Symposium on Field-Programmable Custom Computing Machines (FCCM) . 40--47.","DOI":"10.1109\/FCCM.2016.22"},{"key":"e_1_3_2_1_13_1","unstructured":"Xilinx. 2012. ChipScope Pro Software and Cores: User Guide .  Xilinx. 2012. ChipScope Pro Software and Cores: User Guide ."},{"key":"e_1_3_2_1_14_1","unstructured":"Xilinx. 2016. Integrated Logic Analyzer v6.1: LogiCORE IP Product Guide . http:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/ila\/v6_1\/pg172-ila.pdf . (April 2016).  Xilinx. 2016. Integrated Logic Analyzer v6.1: LogiCORE IP Product Guide . http:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/ila\/v6_1\/pg172-ila.pdf . (April 2016)."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"R. Zhao H. Ng W. Luk and X. Niu. 2018. Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA. arXiv preprint arXiv:1809.03318 (Sept 2018).  R. Zhao H. Ng W. Luk and X. Niu. 2018. Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA. arXiv preprint arXiv:1809.03318 (Sept 2018).","DOI":"10.1109\/FPL.2018.00033"}],"event":{"name":"FPGA '19: The 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Seaside CA USA","acronym":"FPGA '19"},"container-title":["Proceedings of the 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3289602.3293922","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3289602.3293922","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:02:07Z","timestamp":1750208527000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3289602.3293922"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2,20]]},"references-count":15,"alternative-id":["10.1145\/3289602.3293922","10.1145\/3289602"],"URL":"https:\/\/doi.org\/10.1145\/3289602.3293922","relation":{},"subject":[],"published":{"date-parts":[[2019,2,20]]},"assertion":[{"value":"2019-02-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}