{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,4]],"date-time":"2026-04-04T18:12:04Z","timestamp":1775326324583,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":38,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,2,20]],"date-time":"2019-02-20T00:00:00Z","timestamp":1550620800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"The Leverhulme Trust","award":["ECF-2016-289"],"award-info":[{"award-number":["ECF-2016-289"]}]},{"DOI":"10.13039\/501100004815","name":"Isaac Newton Trust","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004815","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,2,20]]},"DOI":"10.1145\/3289602.3293924","type":"proceedings-article","created":{"date-parts":[[2019,2,22]],"date-time":"2019-02-22T22:12:13Z","timestamp":1550873533000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":95,"title":["The P4-&gt;NetFPGA Workflow for Line-Rate Packet Processing"],"prefix":"10.1145","author":[{"given":"Stephen","family":"Ibanez","sequence":"first","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}]},{"given":"Gordon","family":"Brebner","sequence":"additional","affiliation":[{"name":"Xilinx Labs, San Jose, CA, USA"}]},{"given":"Nick","family":"McKeown","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}]},{"given":"Noa","family":"Zilberman","sequence":"additional","affiliation":[{"name":"University of Cambridge, Cambridge, United Kingdom"}]}],"member":"320","published-online":{"date-parts":[[2019,2,20]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.46"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2620728.2620744"},{"key":"e_1_3_2_1_3_1","unstructured":"Philippe Biondi. 2018. Scapy. https:\/\/scapy.net\/  Philippe Biondi. 2018. Scapy. https:\/\/scapy.net\/"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2656877.2656890"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.19"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3234200.3234220"},{"key":"e_1_3_2_1_7_1","unstructured":"Broadcom. 2018. Jerico2 Ethernet Switch Series. https:\/\/www.broadcom.com\/products\/ethernet-connectivity\/switching\/stratadnx\/bcm88690  Broadcom. 2018. Jerico2 Ethernet Switch Series. https:\/\/www.broadcom.com\/products\/ethernet-connectivity\/switching\/stratadnx\/bcm88690"},{"key":"e_1_3_2_1_8_1","unstructured":"Cavium. 2018. XPliant Ethernet Switch Product Family. https:\/\/cavium.com\/xpliant-ethernet-switch-xp60-and-xp70-family.html  Cavium. 2018. XPliant Ethernet Switch Product Family. https:\/\/cavium.com\/xpliant-ethernet-switch-xp60-and-xp70-family.html"},{"key":"e_1_3_2_1_9_1","unstructured":"P4 Language Consortium. 2018. Education Workgroup . Repository https:\/\/github.com\/p4lang\/education\/wiki.  P4 Language Consortium. 2018. Education Workgroup . Repository https:\/\/github.com\/p4lang\/education\/wiki."},{"key":"e_1_3_2_1_11_1","volume-title":"Consensus for Non-Volatile Main Memory. In 2018 IEEE 26th International Conference on Network Protocols (ICNP). IEEE, 406--411","author":"Dang Huynh Tu","year":"2018","unstructured":"Huynh Tu Dang , Jaco Hofmann , Yang Liu , Marjan Radi , Dejan Vucinic , Robert Soul\u00e9 , and Fernando Pedone . 2018 b. Consensus for Non-Volatile Main Memory. In 2018 IEEE 26th International Conference on Network Protocols (ICNP). IEEE, 406--411 . Huynh Tu Dang, Jaco Hofmann, Yang Liu, Marjan Radi, Dejan Vucinic, Robert Soul\u00e9, and Fernando Pedone. 2018b. Consensus for Non-Volatile Main Memory. In 2018 IEEE 26th International Conference on Network Protocols (ICNP). IEEE, 406--411."},{"key":"e_1_3_2_1_12_1","volume-title":"Azure Accelerated Networking: SmartNICs in the Public Cloud. In 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI 18)","author":"Firestone Daniel","year":"2018","unstructured":"Daniel Firestone , Andrew Putnam , Sambhrama Mundkur , Derek Chiou , Alireza Dabagh , Mike Andrewartha , Hari Angepat , Vivek Bhanu , Adrian Caulfield , Eric Chung , 2018 . Azure Accelerated Networking: SmartNICs in the Public Cloud. In 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI 18) , Renton, WA . Daniel Firestone, Andrew Putnam, Sambhrama Mundkur, Derek Chiou, Alireza Dabagh, Mike Andrewartha, Hari Angepat, Vivek Bhanu, Adrian Caulfield, Eric Chung, et almbox. 2018. Azure Accelerated Networking: SmartNICs in the Public Cloud. In 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI 18), Renton, WA ."},{"key":"e_1_3_2_1_13_1","unstructured":"Stephen Ibanez. 2018a. CS344 - Build an Internet Router. https:\/\/build-a-router-instructors.github.io\/  Stephen Ibanez. 2018a. CS344 - Build an Internet Router. https:\/\/build-a-router-instructors.github.io\/"},{"key":"e_1_3_2_1_14_1","unstructured":"Stephen Ibanez. 2018b. P4-&gt;NetFPGA Workflow. https:\/\/github.com\/NetFPGA\/P4-NetFPGA-public\/wiki  Stephen Ibanez. 2018b. P4-&gt;NetFPGA Workflow. https:\/\/github.com\/NetFPGA\/P4-NetFPGA-public\/wiki"},{"key":"e_1_3_2_1_15_1","unstructured":"Stephen Ibanez. 2018c. Tutorial Assignments. https:\/\/github.com\/NetFPGA\/P4-NetFPGA-public\/wiki\/Tutorial-Assignments  Stephen Ibanez. 2018c. Tutorial Assignments. https:\/\/github.com\/NetFPGA\/P4-NetFPGA-public\/wiki\/Tutorial-Assignments"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3132747.3132764"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2834050.2834096"},{"key":"e_1_3_2_1_18_1","volume-title":"Proceedings of the third workshop on Networking and Programming Languages (NetPL) .","author":"Khan Jehandad","year":"2017","unstructured":"Jehandad Khan and Peter Athanas . 2017 . Creating Custom Network Packet Processing Pipelines on HMC-Enabled FPGAs . In Proceedings of the third workshop on Networking and Programming Languages (NetPL) . Jehandad Khan and Peter Athanas. 2017. Creating Custom Network Packet Processing Pipelines on HMC-Enabled FPGAs. In Proceedings of the third workshop on Networking and Programming Languages (NetPL) ."},{"key":"e_1_3_2_1_19_1","unstructured":"Changhoon Kim Anirudh Sivaraman Naga Katta Antonin Bas Advait Dixit and Lawrence J Wobker. 2015. In-band network telemetry via programmable dataplanes. In ACM SIGCOMM .  Changhoon Kim Anirudh Sivaraman Naga Katta Antonin Bas Advait Dixit and Lawrence J Wobker. 2015. In-band network telemetry via programmable dataplanes. In ACM SIGCOMM ."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1355734.1355746"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3098822.3098824"},{"key":"e_1_3_2_1_22_1","unstructured":"NetFPGA.org. 2018. NetFPGA. https:\/\/netfpga.org\/  NetFPGA.org. 2018. NetFPGA. https:\/\/netfpga.org\/"},{"key":"e_1_3_2_1_23_1","unstructured":"Netronome. 2018a. About Agilio SmartNICs. https:\/\/www.netronome.com\/products\/smartnic\/overview\/  Netronome. 2018a. About Agilio SmartNICs. https:\/\/www.netronome.com\/products\/smartnic\/overview\/"},{"key":"e_1_3_2_1_24_1","unstructured":"Netronome. 2018b. P4 Introduction. https:\/\/www.netronome.com\/technology\/p4\/  Netronome. 2018b. P4 Introduction. https:\/\/www.netronome.com\/technology\/p4\/"},{"key":"e_1_3_2_1_25_1","unstructured":"Barefoot Networks. 2018. Tofino. https:\/\/www.barefootnetworks.com\/products\/brief-tofino\/  Barefoot Networks. 2018. Tofino. https:\/\/www.barefootnetworks.com\/products\/brief-tofino\/"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2004.1459818"},{"key":"e_1_3_2_1_27_1","unstructured":"P4.org. 2018a. Announcing P4Runtime. https:\/\/p4.org\/api\/announcing-p4runtime-a-contribution-by-the-p4-api-working-group.html  P4.org. 2018a. Announcing P4Runtime. https:\/\/p4.org\/api\/announcing-p4runtime-a-contribution-by-the-p4-api-working-group.html"},{"key":"e_1_3_2_1_28_1","unstructured":"P4.org. 2018b. behavioral-model. https:\/\/github.com\/p4lang\/behavioral-model  P4.org. 2018b. behavioral-model. https:\/\/github.com\/p4lang\/behavioral-model"},{"key":"e_1_3_2_1_29_1","unstructured":"P4.org. 2018c. Portable Switch Architecture (PSA). https:\/\/p4.org\/p4-spec\/docs\/PSA.html  P4.org. 2018c. Portable Switch Architecture (PSA). https:\/\/p4.org\/p4-spec\/docs\/PSA.html"},{"key":"e_1_3_2_1_30_1","first-page":"117","article-title":"The Design and Implementation of Open vSwitch","volume":"15","author":"Pfaff Ben","year":"2015","unstructured":"Ben Pfaff , Justin Pettit , Teemu Koponen , Ethan J Jackson , Andy Zhou , Jarno Rajahalme , Jesse Gross , Alex Wang , Joe Stringer , Pravin Shelar , 2015 . The Design and Implementation of Open vSwitch .. In NSDI , Vol. 15. 117 -- 130 . Ben Pfaff, Justin Pettit, Teemu Koponen, Ethan J Jackson, Andy Zhou, Jarno Rajahalme, Jesse Gross, Alex Wang, Joe Stringer, Pravin Shelar, et almbox. 2015. The Design and Implementation of Open vSwitch.. In NSDI, Vol. 15. 117--130.","journal-title":"NSDI"},{"key":"e_1_3_2_1_31_1","volume-title":"2018 IEEE 26th International Conference on Network Protocols (ICNP). IEEE, 418--423","author":"Desmouceaux Yoann","year":"2018","unstructured":"Beno^it Pit-Claudel, Yoann Desmouceaux , Pierre Pfister , Mark Townsley , and Thomas Clausen . 2018 . Stateless Load-Aware Load Balancing in P4 . In 2018 IEEE 26th International Conference on Network Protocols (ICNP). IEEE, 418--423 . Beno^it Pit-Claudel, Yoann Desmouceaux, Pierre Pfister, Mark Townsley, and Thomas Clausen. 2018. Stateless Load-Aware Load Balancing in P4. In 2018 IEEE 26th International Conference on Network Protocols (ICNP). IEEE, 418--423."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174270"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2934872.2934886"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2008.46"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/2934872.2934900"},{"key":"e_1_3_2_1_36_1","volume-title":"2017 USENIX Annual Technical Conference (USENIX ATC 17)","author":"Sultana Nik","year":"2017","unstructured":"Nik Sultana , Salvator Galea , David Greaves , Marcin W\u00f3jcik , Jonny Shipton , Richard Clegg , Luo Mai , Pietro Bressana , Robert Soul\u00e9 , Richard Mortier , 2017 . Emu: Rapid prototyping of networking services . In 2017 USENIX Annual Technical Conference (USENIX ATC 17) . 459--471. Nik Sultana, Salvator Galea, David Greaves, Marcin W\u00f3jcik, Jonny Shipton, Richard Clegg, Luo Mai, Pietro Bressana, Robert Soul\u00e9, Richard Mortier, et almbox. 2017. Emu: Rapid prototyping of networking services. In 2017 USENIX Annual Technical Conference (USENIX ATC 17). 459--471."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/3050220.3050234"},{"key":"e_1_3_2_1_38_1","unstructured":"Xilinx. 2018. SDNet. https:\/\/www.xilinx.com\/products\/design-tools\/software-zone\/sdnet.html  Xilinx. 2018. SDNet. https:\/\/www.xilinx.com\/products\/design-tools\/software-zone\/sdnet.html"},{"key":"e_1_3_2_1_39_1","volume-title":"NetFPGA SUME: Toward 100 Gbps as research commodity","author":"Zilberman Noa","year":"2014","unstructured":"Noa Zilberman , Yury Audzevich , G Adam Covington , and Andrew W Moore . 2014. NetFPGA SUME: Toward 100 Gbps as research commodity . IEEE micro, Vol. 34 , 5 ( 2014 ), 32--41. Noa Zilberman, Yury Audzevich, G Adam Covington, and Andrew W Moore. 2014. NetFPGA SUME: Toward 100 Gbps as research commodity. IEEE micro, Vol. 34, 5 (2014), 32--41."}],"event":{"name":"FPGA '19: The 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","location":"Seaside CA USA","acronym":"FPGA '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3289602.3293924","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3289602.3293924","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:02:07Z","timestamp":1750208527000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3289602.3293924"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2,20]]},"references-count":38,"alternative-id":["10.1145\/3289602.3293924","10.1145\/3289602"],"URL":"https:\/\/doi.org\/10.1145\/3289602.3293924","relation":{},"subject":[],"published":{"date-parts":[[2019,2,20]]},"assertion":[{"value":"2019-02-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}