{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:31:46Z","timestamp":1750221106408,"version":"3.41.0"},"reference-count":78,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2018,12,31]],"date-time":"2018-12-31T00:00:00Z","timestamp":1546214400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Science Foundation of China","doi-asserted-by":"crossref","award":["61872155 and 61472151"],"award-info":[{"award-number":["61872155 and 61472151"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Pre-research Project of Beifang","award":["FFZ-1601"],"award-info":[{"award-number":["FFZ-1601"]}]},{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program","doi-asserted-by":"crossref","award":["2018YFB1003600"],"award-info":[{"award-number":["2018YFB1003600"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2018,12,31]]},"abstract":"<jats:p>Data persistence is necessary for many in-memory applications. However, the disk-based data persistence largely slows down in-memory applications. Emerging non-volatile memory (NVM) offers an opportunity to achieve in-memory data persistence at the DRAM-level performance. Nevertheless, NVM typically requires a software library to operate NVM data, which brings significant overhead.<\/jats:p>\n          <jats:p>\n            This article demonstrates that a hardware-based high-frequency checkpointing mechanism can be used to achieve efficient in-memory data persistence on NVM. To maintain checkpoint consistency, traditional logging and copy-on-write techniques incur excessive NVM writes that impair both performance and endurance of NVM; recent work attempts to solve the issue but requires a large amount of metadata in the memory controller. Hence, we design a new\n            <jats:italic>dual-page checkpointing<\/jats:italic>\n            system, which achieves low metadata cost and eliminates most excessive NVM writes at the same time. It breaks the traditional trade-off between metadata space cost and extra data writes. Our solution outperforms the state-of-the-art NVM software libraries by 13.6\u00d7 in throughput, and leads to 34% less NVM wear-out and 1.28\u00d7 higher throughput than state-of-the-art hardware checkpointing solutions, according to our evaluation with OLTP, graph computing, and machine-learning workloads.\n          <\/jats:p>","DOI":"10.1145\/3291057","type":"journal-article","created":{"date-parts":[[2019,1,8]],"date-time":"2019-01-08T15:53:12Z","timestamp":1546962792000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Dual-Page Checkpointing"],"prefix":"10.1145","volume":"15","author":[{"given":"Song","family":"Wu","sequence":"first","affiliation":[{"name":"Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fang","family":"Zhou","sequence":"additional","affiliation":[{"name":"Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiang","family":"Gao","sequence":"additional","affiliation":[{"name":"Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hai","family":"Jin","sequence":"additional","affiliation":[{"name":"Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinglei","family":"Ren","sequence":"additional","affiliation":[{"name":"Microsoft Research, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,1,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006248"},{"volume-title":"Proc. IEEE 98","year":"2010","author":"Akinaga H.","key":"e_1_2_1_2_1"},{"key":"e_1_2_1_3_1","unstructured":"Alluxio Open Foundation. 2017. Open Source Memory Speed Virtual Distributed Storage. Retrieved from http:\/\/www.alluxio.org\/.  Alluxio Open Foundation. 2017. Open Source Memory Speed Virtual Distributed Storage. Retrieved from http:\/\/www.alluxio.org\/."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463585.2463589"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2723372.2742797"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1177\/1094342014532297"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.14778\/2735479.2735483"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488873"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950380"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629589"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654117"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592814"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-013-0884-0"},{"key":"e_1_2_1_14_1","first-page":"1","article-title":"Detection and correction of silent data corruption for large-scale high-performance computing. In Proceedings of the International Conference on High Performance Computing","volume":"78","author":"Fiala David","year":"2012","journal-title":"Networking, Storage and Analysis."},{"key":"e_1_2_1_15_1","unstructured":"Balint Fleischer. 2016. Storage Class Memory in Scalable Cognitive Systems. Keynote in Flash Memory Summit. Retrieved from https:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2016\/20160809_Keynote5_Huawei_Fleischer.pdf.  Balint Fleischer. 2016. Storage Class Memory in Scalable Cognitive Systems. Keynote in Flash Memory Summit. Retrieved from https:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2016\/20160809_Keynote5_Huawei_Fleischer.pdf."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/1924943.1924948"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751212"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/945445.945450"},{"volume-title":"Proceedings of the 31st Symposium on Mass Storage Systems and Technologies (MSST\u201915)","author":"Giles E. R.","key":"e_1_2_1_19_1"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522338"},{"key":"e_1_2_1_21_1","unstructured":"Intel. 2016. The NVM Library. Retrieved from http:\/\/pmem.io\/.  Intel. 2016. The NVM Library. Retrieved from http:\/\/pmem.io\/."},{"key":"e_1_2_1_22_1","unstructured":"Intel. 2017. Intel Optane Technology. Retrieved from http:\/\/www.intel.com\/content\/www\/us\/en\/architecture-and-technology\/intel-optane-technology.html.  Intel. 2017. Intel Optane Technology. Retrieved from http:\/\/www.intel.com\/content\/www\/us\/en\/architecture-and-technology\/intel-optane-technology.html."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337190"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.69"},{"volume-title":"Memory-Driven Computing. In Proceedings of the 15th USENIX Conference on File and Storage Technologies (FAST\u201917)","year":"2017","author":"Keeton Kimberly","key":"e_1_2_1_25_1"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872381"},{"volume-title":"Proceedings of the 10th USENIX Conference on Operating Systems Design and Implementation (OSDI\u201912)","year":"2012","author":"Kyrola Aapo","key":"e_1_2_1_27_1"},{"volume-title":"Proceedings of the 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS\u201913)","author":"K\u00fclt\u00fcrsay E.","key":"e_1_2_1_28_1"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.24"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3132747.3132756"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2670979.2670985"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.5555\/2685048.2685095"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463676.2465248"},{"volume-title":"Proceedings of the 13th Usenix Conference on Networked Systems Design and Implementation (NSDI\u201916)","year":"2016","author":"Lin Wei","key":"e_1_2_1_35_1"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037714"},{"key":"e_1_2_1_37_1","first-page":"1","article-title":"Survive: Pointer-based in-DRAM incremental checkpointing for low-cost data persistence and rollback-recovery","volume":"99","author":"Mirhosseini A.","year":"2016","journal-title":"IEEE Comput. Architect. Lett. PP"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2524211.2524216"},{"volume-title":"Mount and Sunil Arya","year":"1998","author":"David","key":"e_1_2_1_39_1"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.2014.2321376"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037730"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151018"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.5555\/1298455.1298457"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/2043556.2043560"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2806887"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00778-015-0411-4"},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2402435"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.5555\/1855741.1855752"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545228"},{"volume-title":"Proceedings of the 29th Annual International Symposium on Computer Architecture. 111--122","author":"Prvulovic M.","key":"e_1_2_1_51_1"},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995911"},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/3124680.3124729"},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830802"},{"key":"e_1_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750379"},{"key":"e_1_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.8"},{"key":"e_1_2_1_60_1","unstructured":"Neuvonen Simo Wolski Antoni Manner Markk and Raatikka Vilho. {n.d.}. Telecom Application Transaction Processing Benchmark. Retrieved from http:\/\/tatpbenchmark.sourceforge.net\/.  Neuvonen Simo Wolski Antoni Manner Markk and Raatikka Vilho. {n.d.}. Telecom Application Transaction Processing Benchmark. Retrieved from http:\/\/tatpbenchmark.sourceforge.net\/."},{"volume-title":"Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA\u201902)","author":"Sorin Daniel J.","key":"e_1_2_1_61_1"},{"volume-title":"SPEC CPU 2006","year":"2006","author":"Standard Performance Evaluation Corporation","key":"e_1_2_1_62_1"},{"key":"e_1_2_1_63_1","first-page":"184","article-title":"An integrated simulation infrastructure for the entire memory hierarchy: Cache, DRAM, nonvolatile memory, and disk","volume":"17","author":"Stevens Jim","year":"2013","journal-title":"Intel. Technol. J."},{"volume-title":"Proceedings of the 4th Workshop on Interactions of NVM\/Flash with Operating Systems and Workloads.","year":"2016","author":"Talagala Nisha","key":"e_1_2_1_64_1"},{"key":"e_1_2_1_65_1","unstructured":"The Transaction Processing Council. 2017. TPC-C benchmark Version 5. Retrieved from http:\/\/www.tpc.org\/tpcc\/.  The Transaction Processing Council. 2017. TPC-C benchmark Version 5. Retrieved from http:\/\/www.tpc.org\/tpcc\/."},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522713"},{"volume-title":"Proceedings of the 9th USENIX Conference on File and Stroage Technologies (FAST\u201911)","year":"1960","author":"Venkataraman Shivaram","key":"e_1_2_1_67_1"},{"key":"e_1_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540710"},{"key":"e_1_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.45"},{"key":"e_1_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950379"},{"key":"e_1_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.5555\/1782174.1782206"},{"key":"e_1_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2008.172"},{"volume-title":"Continuous Applications: Evolving Streaming in Apache Spark 2.0: A foundation for end-to-end real-time applications. Databricks Engineering Blog.","year":"2016","author":"Zaharia Matei","key":"e_1_2_1_73_1"},{"volume-title":"Proceedings of the 9th USENIX Conference on Networked Systems Design and Implementation (NSDI\u201912)","year":"2012","author":"Zaharia Matei","key":"e_1_2_1_74_1"},{"key":"e_1_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694370"},{"volume-title":"Proceedings of the IEEE\/IFIP 42nd International Conference on Dependable Systems and Networks Workshops. 1--6.","author":"Zheng Gengbin","key":"e_1_2_1_76_1"},{"key":"e_1_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.5555\/2685048.2685085"},{"key":"e_1_2_1_78_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451512.2451547"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3291057","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3291057","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:01:52Z","timestamp":1750208512000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3291057"}},"subtitle":["An Architectural Approach to Efficient Data Persistence for In-Memory Applications"],"short-title":[],"issued":{"date-parts":[[2018,12,31]]},"references-count":78,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2018,12,31]]}},"alternative-id":["10.1145\/3291057"],"URL":"https:\/\/doi.org\/10.1145\/3291057","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2018,12,31]]},"assertion":[{"value":"2018-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-01-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}