{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T15:05:53Z","timestamp":1762009553924,"version":"build-2065373602"},"reference-count":35,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2018,12,31]],"date-time":"2018-12-31T00:00:00Z","timestamp":1546214400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"ECOSCALE","award":["671632"],"award-info":[{"award-number":["671632"]}]},{"name":"MECCA","award":["340328"],"award-info":[{"award-number":["340328"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2018,12,31]]},"abstract":"<jats:p>\n            DRAM caches have shown excellent potential in capturing the spatial and temporal data locality of applications capitalizing on advances of 3D-stacking technology; however, they are still far from their ideal performance. Besides the unavoidable DRAM access to fetch the requested data, tag access is in the critical path, adding significant latency and energy costs. Existing approaches are not able to remove these overheads and in some cases limit DRAM cache design options. For instance, caching DRAM cache tags adds constant latency to every access; accessing the DRAM cache using the TLB calls for OS support and DRAM cachelines as large as a page; reusing the last-level cache (LLC) tags to access the DRAM cache limits LLC performance as it requires indexing the LLC using higher-order address bits. In this article, we introduce\n            <jats:italic>Decoupled Fused Cache<\/jats:italic>\n            , a DRAM cache design that alleviates the cost of tag accesses by fusing DRAM cache tags with the tags of the on-chip LLC without affecting LLC performance. In essence, the\n            <jats:italic>Decoupled Fused Cache<\/jats:italic>\n            relies in most cases on the LLC tag access to retrieve the required information for accessing the DRAM cache while avoiding additional overheads. Compared to current DRAM cache designs of the same cacheline size,\n            <jats:italic>Decoupled Fused Cache<\/jats:italic>\n            improves system performance by 6% on average and by 16% to 18% for large cacheline sizes. Finally,\n            <jats:italic>Decoupled Fused Cache<\/jats:italic>\n            reduces DRAM cache traffic by 18% and DRAM cache energy consumption by 7%.\n          <\/jats:p>","DOI":"10.1145\/3293447","type":"journal-article","created":{"date-parts":[[2019,1,8]],"date-time":"2019-01-08T15:53:12Z","timestamp":1546962792000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Decoupled Fused Cache"],"prefix":"10.1145","volume":"15","author":[{"given":"Evangelos","family":"Vasilakis","sequence":"first","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vassilis","family":"Papaefstathiou","sequence":"additional","affiliation":[{"name":"Foundation for Research and Technology Hellas (FORTH), Heraklion, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pedro","family":"Trancoso","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ioannis","family":"Sourdis","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,1,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3046680"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750387"},{"volume-title":"2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201916)","author":"Chou C.","key":"e_1_2_1_5_1"},{"key":"e_1_2_1_6_1","first-page":"1","article-title":"Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor","volume":"7","author":"Edmondson John H.","year":"1995","journal-title":"Digital Tech. J."},{"volume-title":"International Symposium on High-Performance Computer Architecture (HPCA\u201910)","author":"Genbrugge D.","key":"e_1_2_1_7_1"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.36"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593197"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_2_1_11_1","unstructured":"HP-Labs. 2017. An integrated cache and memory access time cycle time area leakage and dynamic power model. Retrieved from http:\/\/www.hpl.hp.com\/research\/cacti\/.  HP-Labs. 2017. An integrated cache and memory access time cycle time area leakage and dynamic power model. Retrieved from http:\/\/www.hpl.hp.com\/research\/cacti\/."},{"volume-title":"The 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-49\u201916)","year":"1956","author":"Huang C.-C.","key":"e_1_2_1_12_1"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628089"},{"key":"e_1_2_1_14_1","unstructured":"MIPS Technologies Inc. 1996. MIPS R10000 Microprocessor Users Manual. Retrieved from ftp:\/\/ftp.sgi.com\/sgi\/doc\/R10000\/User_Manual\/t5.ver.2.0.book.pdf.  MIPS Technologies Inc. 1996. MIPS R10000 Microprocessor Users Manual. Retrieved from ftp:\/\/ftp.sgi.com\/sgi\/doc\/R10000\/User_Manual\/t5.ver.2.0.book.pdf."},{"key":"e_1_2_1_15_1","unstructured":"Intel. 2018. Intel 64 and IA-32 Architectures Software Developer Manuals. Retrieved from https:\/\/software.intel.com\/en-us\/articles\/intel-sdm.  Intel. 2018. Intel 64 and IA-32 Architectures Software Developer Manuals. Retrieved from https:\/\/software.intel.com\/en-us\/articles\/intel-sdm."},{"volume-title":"2016 IEEE International Symposium on High Performance Computer Architecture (HPCA\u201916)","author":"Jang H.","key":"e_1_2_1_16_1"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.51"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485957"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750383"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.25"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155673"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2012.2"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2546249"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250713"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.30"},{"key":"e_1_2_1_29_1","unstructured":"Center for Manycore Programming Seoul National University. 2015. SNU NPB Suite. Retrieved from http:\/\/aces.snu.ac.kr\/software\/snu-npb\/.  Center for Manycore Programming Seoul National University. 2015. SNU NPB Suite. Retrieved from http:\/\/aces.snu.ac.kr\/software\/snu-npb\/."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192072"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/635506.605403"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.31"},{"key":"e_1_2_1_33_1","doi-asserted-by":"crossref","unstructured":"E. Vasilakis V. Papaefstathiou P. Trancoso and I. Sourdis. 2018. FusionCache: Using LLC tags for DRAM cache. In Design Automation Test in Europe (DATE\u201918). 593--596.  E. Vasilakis V. Papaefstathiou P. Trancoso and I. Sourdis. 2018. FusionCache: Using LLC tags for DRAM cache. In Design Automation Test in Europe (DATE\u201918). 593--596.","DOI":"10.23919\/DATE.2018.8342077"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124555"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3293447","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3293447","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:02:01Z","timestamp":1750208521000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3293447"}},"subtitle":["Fusing a Decoupled LLC with a DRAM Cache"],"short-title":[],"issued":{"date-parts":[[2018,12,31]]},"references-count":35,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2018,12,31]]}},"alternative-id":["10.1145\/3293447"],"URL":"https:\/\/doi.org\/10.1145\/3293447","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2018,12,31]]},"assertion":[{"value":"2018-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-01-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}