{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,25]],"date-time":"2026-02-25T23:22:45Z","timestamp":1772061765645,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":90,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,4,4]],"date-time":"2019-04-04T00:00:00Z","timestamp":1554336000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,4,4]]},"DOI":"10.1145\/3297858.3304010","type":"proceedings-article","created":{"date-parts":[[2019,4,4]],"date-time":"2019-04-04T18:38:43Z","timestamp":1554403123000},"page":"271-286","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":26,"title":["Just-In-Time Compilation for Verilog"],"prefix":"10.1145","author":[{"given":"Eric","family":"Schkufza","sequence":"first","affiliation":[{"name":"VMware Research, palo alto, CA, USA"}]},{"given":"Michael","family":"Wei","sequence":"additional","affiliation":[{"name":"VMware Research, palo alto, CA, USA"}]},{"given":"Christopher J.","family":"Rossbach","sequence":"additional","affiliation":[{"name":"University of Texas Austin &amp; VMware Research, Austin, TX, USA"}]}],"member":"320","published-online":{"date-parts":[[2019,4,4]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"{n. d.}. AppArmor. http:\/\/www.xilinx.com\/products\/designtools\/ software-zone\/sdaccel.html."},{"key":"e_1_3_2_1_2_1","volume-title":"d.}. Cadence Palladium XP II Verification Computing Platform. https:\/\/www.cadence.com\/content\/dam\/cadence-www\/global\/ enUS\/documents\/tools\/system-design-verification\/palladium-xpiitb. pdf. (Accessed","year":"2019","unstructured":"{n. d.}. Cadence Palladium XP II Verification Computing Platform. https:\/\/www.cadence.com\/content\/dam\/cadence-www\/global\/ enUS\/documents\/tools\/system-design-verification\/palladium-xpiitb. pdf. (Accessed January 2019)."},{"key":"e_1_3_2_1_3_1","volume-title":"d.}. Debian -- Details of Package fpgatools. https:\/\/ packages.debian.org\/stretch\/fpgatools. (Accessed","year":"2018","unstructured":"{n. d.}. Debian -- Details of Package fpgatools. https:\/\/ packages.debian.org\/stretch\/fpgatools. (Accessed July 2018)."},{"key":"e_1_3_2_1_4_1","volume-title":"d.}. FPGAMiner. https:\/\/github.com\/fpgaminer\/Open-Source- FPGA-Bitcoin-Miner. (Accessed","year":"2018","unstructured":"{n. d.}. FPGAMiner. https:\/\/github.com\/fpgaminer\/Open-Source- FPGA-Bitcoin-Miner. (Accessed July 2018)."},{"key":"e_1_3_2_1_5_1","volume-title":"d.}. SymbiFlow. https:\/\/symbiflow.github.io\/. (Accessed","year":"2018","unstructured":"{n. d.}. SymbiFlow. https:\/\/symbiflow.github.io\/. (Accessed July 2018)."},{"key":"e_1_3_2_1_6_1","volume-title":"IEEE Standard for Verilog Hardware Description Language","year":"2005","unstructured":"2006. IEEE Standard for Verilog Hardware Description Language. IEEE Std 1364--2005 (Revision of IEEE Std 1364--2001) (2006), 1--560."},{"key":"e_1_3_2_1_7_1","volume-title":"IEEE Standard VHDL Language Reference Manual","year":"2008","unstructured":"2009. IEEE Standard VHDL Language Reference Manual. IEEE Std 1076--2008 (Revision of IEEE Std 1076--2002) (Jan 2009), c1--626."},{"key":"e_1_3_2_1_8_1","unstructured":"2017. Avalon Interface Specifications."},{"key":"e_1_3_2_1_9_1","unstructured":"2017. Device Handbook - Altera Cyclone V."},{"key":"e_1_3_2_1_10_1","unstructured":"2017. Intel unveils new Xeon chip with integrated FPGA touts 20x performance boost - ExtremeTech. https:\/\/www.extremetech.com\/ extreme\/184828-intel-unveils-new-xeon-chip-with-integrated-fpgatouts- 20x-performance-boost"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950421"},{"key":"e_1_3_2_1_12_1","volume-title":"Bazel: Correct, reproducible, fast builds for everyone. https:\/\/bazel.io","author":"K Aehlig","year":"2016","unstructured":"K Aehlig et al. 2016. Bazel: Correct, reproducible, fast builds for everyone. https:\/\/bazel.io"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.40"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1869459.1869469"},{"key":"e_1_3_2_1_15_1","volume-title":"Wunsch","author":"Needleman Saul B.","year":"1970","unstructured":"Saul B. Needleman and Christian D.Wunsch. 1970. A General Method Applicable to Search for Similarities in Amino Acid Sequence of 2 Proteins. Journal of molecular biology 48 (04 1970), 443--53."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.25"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/647923.741195"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689086"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554787"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195647"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2597917.2597929"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/2492708.2492853"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485945"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/1457713"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/2685817"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847339"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2006.02.009"},{"key":"e_1_3_2_1_29_1","unstructured":"Amazon EC2. 2017. Amazon EC2 F1 Instances."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2889160.2889222"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2008.48"},{"key":"e_1_3_2_1_32_1","unstructured":"K Funk et al. 2016. icecream. https:\/\/github.com\/icecc\/icecream"},{"key":"e_1_3_2_1_33_1","unstructured":"GNU. {n. d.}. GTKWave. http:\/\/gtkwave.sourceforge.net. (Accessed July 2018)."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2012.03.002"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.5555\/2650280.2650390"},{"key":"e_1_3_2_1_36_1","unstructured":"Arria V Device Handbook. 2012. Volume 1: Device Overview and Datasheet. (2012)."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.5555\/993815"},{"key":"e_1_3_2_1_38_1","unstructured":"SRC Computers Inc. 2006. Carte Programming Environment."},{"key":"e_1_3_2_1_39_1","unstructured":"Intel. 2018. Intel Quartus Prime Software. https: \/\/www.altera.com\/products\/design-software\/fpga-design\/quartusprime\/ download.html"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.14778\/3137628.3137632"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.5555\/2930611.2930639"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1968502.1968511"},{"key":"e_1_3_2_1_43_1","volume-title":"Field Programmable Logic and Applications, 2005. International Conference on. 223--228","author":"Kalte H.","unstructured":"H. Kalte and M. Porrmann. 2005. Context saving and restoring for multitasking in reconfigurable systems. In Field Programmable Logic and Applications, 2005. International Conference on. 223--228."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/2168836.2168866"},{"key":"e_1_3_2_1_45_1","volume-title":"Hoplite: Building austere overlay NoCs for FPGAs","author":"Kapre Nachiket","year":"2015","unstructured":"Nachiket Kapre and Jan Gray. 2015. Hoplite: Building austere overlay NoCs for FPGAs. In FPL. IEEE, 1--8."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577353"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.5555\/3291168.3291177"},{"key":"e_1_3_2_1_48_1","volume-title":"Version 1.0","author":"Khronos Group 2009.","unstructured":"Khronos Group 2009. The OpenCL Specification, Version 1.0. Khronos Group."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/2746404"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145728"},{"key":"e_1_3_2_1_51_1","volume-title":"Proceedings of the Linux symposium","volume":"1","author":"Kivity Avi","year":"2007","unstructured":"Avi Kivity, Yaniv Kamay, Dor Laor, Uri Lublin, and Anthony Liguori. 2007. kvm: the Linux virtual machine monitor. In Proceedings of the Linux symposium, Vol. 1. 225--230."},{"key":"e_1_3_2_1_52_1","volume-title":"Lemieux","author":"Koch Dirk","year":"2013","unstructured":"Dirk Koch, Christian Beckhoff, and Guy G. F. Lemieux. 2013. An efficient FPGA overlay for portable custom instruction set extensions. In FPL. IEEE, 1--8."},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.20"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3192366.3192379"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2004.840303"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1155\/2012\/439141"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.64"},{"key":"e_1_3_2_1_58_1","first-page":"1289","article-title":"Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems","volume":"26","author":"Lee Trong-Yen","year":"2010","unstructured":"Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, and Chia-Chun Tsai. 2010. Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems. J. Inf. Sci. Eng. 26 (2010), 1289--1305.","journal-title":"J. Inf. Sci. Eng."},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.5555\/795659.795885"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750416"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1145\/1596532.1596540"},{"key":"e_1_3_2_1_62_1","unstructured":"Microsoft. 2017. Microsoft Azure Goes Back To Rack Servers With Project Olympus."},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168917.1168878"},{"key":"e_1_3_2_1_64_1","unstructured":"Nicholas Moore Albert Conti Miriam Leeser Benjamin Cordes and Laurie Smith King. 2007. An extensible framework for application portability between reconfigurable supercomputing architectures."},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2004.1459818"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847337"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2013.6567578"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.5555\/1097107.1097134"},{"key":"e_1_3_2_1_69_1","unstructured":"M Pool et al. 2016. distcc: A free distributed C\/C++ compiler system. https:\/\/github.com\/distcc\/distcc"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080256"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665678"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2009.30"},{"key":"e_1_3_2_1_73_1","unstructured":"J. Russell and R. Cohn. 2012. Icarus Verilog. Book on Demand. https: \/\/books.google.co.uk\/books?id=ZNanMQEACAAJ"},{"key":"e_1_3_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.5120\/8738-2991"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723129"},{"key":"e_1_3_2_1_76_1","unstructured":"WSnyder D Galbi and PWasson. 2018. Verilator. https:\/\/veripool.org\/ wiki\/verilator"},{"key":"e_1_3_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1145\/1331331.1331338"},{"key":"e_1_3_2_1_78_1","volume-title":"Brodersen","author":"Kwok-Hay So Hayden","year":"2007","unstructured":"Hayden Kwok-Hay So and Robert W. Brodersen. 2007. BORPH: An Operating System for FPGA-Based Reconfigurable Computers. Ph.D. Dissertation. EECS Department, University of California, Berkeley. http: \/\/www.eecs.berkeley.edu\/Pubs\/TechRpts\/2007\/EECS-2007--92.html"},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847345"},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515770"},{"key":"e_1_3_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.99"},{"key":"e_1_3_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847276"},{"key":"e_1_3_2_1_83_1","volume-title":"Henssonow","author":"Surhone Lambert M.","year":"2010","unstructured":"Lambert M. Surhone, Mariam T. Tennoe, and Susan F. Henssonow. 2010. Node.Js. Betascript Publishing, Mauritius."},{"key":"e_1_3_2_1_84_1","unstructured":"A Tridgell J Rosdahl et al. 2016. ccache: A Fast C\/C++ Compiler Cache. https:\/\/ccache.samba.org"},{"key":"e_1_3_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.5555\/645463.653355"},{"key":"e_1_3_2_1_86_1","volume-title":"Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on. 1--7.","author":"Wassi G.","unstructured":"G. Wassi, Mohamed El Amine Benkhelifa, G. Lawday, F. Verdier, and S. Garcia. 2014. Multi-shape tasks scheduling for online multitasking on FPGAs. In Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on. 1--7."},{"key":"e_1_3_2_1_87_1","volume-title":"ReConFig","author":"Wiersema Tobias","unstructured":"Tobias Wiersema, Ame Bockhorn, and Marco Platzner. 2014. Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA. In ReConFig. IEEE, 1--6."},{"key":"e_1_3_2_1_88_1","unstructured":"Clifford Wolf. {n. d.}. Yosys Open SYnthesis Suite. http:\/\/ www.clifford.at\/yosys\/. (Accessed July 2018)."},{"key":"e_1_3_2_1_89_1","unstructured":"Xilinx. 2018. Vivado Design Suite. https:\/\/www.xilinx.com\/products\/ design-tools\/vivado.html"},{"key":"e_1_3_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"}],"event":{"name":"ASPLOS '19: Architectural Support for Programming Languages and Operating Systems","location":"Providence RI USA","acronym":"ASPLOS '19","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3297858.3304010","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3297858.3304010","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:53:14Z","timestamp":1750204394000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3297858.3304010"}},"subtitle":["A New Technique for Improving the FPGA Programming Experience"],"short-title":[],"issued":{"date-parts":[[2019,4,4]]},"references-count":90,"alternative-id":["10.1145\/3297858.3304010","10.1145\/3297858"],"URL":"https:\/\/doi.org\/10.1145\/3297858.3304010","relation":{},"subject":[],"published":{"date-parts":[[2019,4,4]]},"assertion":[{"value":"2019-04-04","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}