{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:42:04Z","timestamp":1773247324750,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":45,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,4,4]],"date-time":"2019-04-04T00:00:00Z","timestamp":1554336000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Intel"},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1439021 1439057 1409095 1626251 1629915 1629129 1526750"],"award-info":[{"award-number":["1439021 1439057 1409095 1626251 1629915 1629129 1526750"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"NRF","award":["2016R1C1B2015312 2015M3C4A7065645"],"award-info":[{"award-number":["2016R1C1B2015312 2015M3C4A7065645"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,4,4]]},"DOI":"10.1145\/3297858.3304035","type":"proceedings-article","created":{"date-parts":[[2019,4,4]],"date-time":"2019-04-04T18:38:43Z","timestamp":1554403123000},"page":"955-969","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":31,"title":["SOML Read"],"prefix":"10.1145","author":[{"given":"Chun-Yi","family":"Liu","sequence":"first","affiliation":[{"name":"Pennsylvania State University, state college, PA, USA"}]},{"given":"Jagadish B.","family":"Kotra","sequence":"additional","affiliation":[{"name":"AMD Research, Austin, TX, USA"}]},{"given":"Myoungsoo","family":"Jung","sequence":"additional","affiliation":[{"name":"Korea Advanced Institute of Science and Technology, KAIST, Daejeon, South Korea"}]},{"given":"Mahmut T.","family":"Kandemir","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, state college, PA, USA"}]},{"given":"Chita R.","family":"Das","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, state college, PA, USA"}]}],"member":"320","published-online":{"date-parts":[[2019,4,4]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/2492708.2492838"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.49"},{"key":"e_1_3_2_1_3_1","volume-title":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA). 551--563","author":"Cai Y.","unstructured":"Y. Cai, Y. Luo, E. F. Haratsch, K. Mai, and O. Mutlu. 2015. Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. In 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA). 551--563."},{"key":"e_1_3_2_1_4_1","volume-title":"2013 IEEE 31st International Conference on Computer Design (ICCD). IEEE, 123--130","author":"Cai Yu","unstructured":"Yu Cai, Onur Mutlu, Erich~F. Haratsch, and Ken Mai. {n. d.} b. Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation. In 2013 IEEE 31st International Conference on Computer Design (ICCD). IEEE, 123--130."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2542215"},{"key":"e_1_3_2_1_6_1","unstructured":"Hyeokjun Choe Seil Lee Seongsik Park Sei~Joon Kim Eui-Young Chung and Sungroh Yoon. 2016. Near-Data Processing for Machine Learning. http:\/\/arxiv.org\/abs\/1610.02273. (2016)."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037728"},{"key":"e_1_3_2_1_8_1","volume-title":"MDACache:Caching for Multi-Dimensional-Access Memories. In The 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-50)","author":"George Sumitha","year":"2018","unstructured":"Sumitha George, Minli Liao, Huaipan Jiang, Jagadish~B. Kotra, Mahmut Kandemir, Jack Sampson, and Vijaykrishnan Narayanan. 2018. MDACache:Caching for Multi-Dimensional-Access Memories. In The 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-50)."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508271"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995912"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062960"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1721695.1721706"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665715"},{"key":"e_1_3_2_1_14_1","volume-title":"2016 IEEE International Solid-State Circuits Conference (ISSCC).","author":"Kang D.","unstructured":"D. Kang, W. Jeong, C. Kim, D. H. Kim, Y. S. Cho, K. T. Kang, J. Ryu, K. M. Kang, S. Lee, W. Kim, H. Lee, J. Yu, N. Choi, D. S. Jang, J. D. Ihm, D. Kim, Y. S. Min, M. S. Kim, A. S. Park, J. I. Son, I. M. Kim, P. Kwak, B. K. Jung, D. S. Lee, H. Kim, H. J. Yang, D. S. Byeon, K. T. Park, K. H. Kyung, and J. H. Choi. 2016. 7.1 256Gb 3b\/cell V-NAND flash memory with 48 stacked WL layers. In 2016 IEEE International Solid-State Circuits Conference (ISSCC)."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870331"},{"key":"e_1_3_2_1_16_1","volume-title":"2009 Symposium on VLSI Technology .","author":"Kim Wonjoo","unstructured":"Wonjoo Kim, Sangmoo Choi, Junghun Sung, Taehee Lee, C. Park, Hyoungsoo Ko, Juhwan Jung, Inkyong Yoo, and Y. Park. 2009. Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storage. In 2009 Symposium on VLSI Technology ."},{"key":"e_1_3_2_1_17_1","volume-title":"Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) .","author":"Kislal O.","unstructured":"O. Kislal, M. T. Kandemir, and J. Kotra. 2016. Cache-Aware Approximate Computing for Decision Tree Learning. In Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) ."},{"key":"e_1_3_2_1_18_1","volume-title":"Proceedings of 25th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS) .","author":"Kotra Jagadish","unstructured":"Jagadish Kotra, D. Guttman, Nachiappan. C. N., M. T. Kandemir, and C. R. Das. 2017a. Quantifying the Potential Benefits of On-chip Near-Data Computing in Manycore Processors. In Proceedings of 25th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS) ."},{"key":"e_1_3_2_1_19_1","volume-title":"Proceedings of IEEE International Symposium on Workload Characterization (IISWC) .","author":"Kotra Jagadish","unstructured":"Jagadish Kotra, S. Kim, K. Madduri, and M. T. Kandemir. 2017b. Congestion-aware memory management on NUMA platforms: A VMware ESXi case study. In Proceedings of IEEE International Symposium on Workload Characterization (IISWC) ."},{"key":"e_1_3_2_1_20_1","volume-title":"Proceedings of IEEE International Parallel and Distributed Processing Symposium (IPDPS) .","author":"Kotra J. B.","unstructured":"J. B. Kotra, M. Arjomand, D. Guttman, M. T. Kandemir, and C. R. Das. 2016. Re-NUCA: A Practical NUCA Architecture for ReRAM Based Last-Level Caches. In Proceedings of IEEE International Parallel and Distributed Processing Symposium (IPDPS) ."},{"key":"e_1_3_2_1_21_1","volume-title":"CHAMELEON: A Dynamically Reconfigurable Heterogeneous Memory System. In The 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-50)","author":"Kotra B.","year":"2018","unstructured":"Jagadish~B. Kotra, Haibo Zhang, Alaa Alameldeen, Chris Wilkerson, and Mahmut~T. Kandemir. 2018. CHAMELEON: A Dynamically Reconfigurable Heterogeneous Memory System. In The 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-50)."},{"key":"e_1_3_2_1_22_1","volume-title":"2016 IEEE International Symposium on Workload Characterization (IISWC) .","author":"Kwon Miryeong","year":"2017","unstructured":"Miryeong Kwon, Jie Zhang, Gyuyoung Park, Wonil Choi, David Donofrio, John Shalf, Mahmut Kandemir, and Myoungsoo Jung. 2017. TraceTracker: Hardware\/Software Co-Evaluation for Large-Scale I\/O Workload Reconstruction. In 2016 IEEE International Symposium on Workload Characterization (IISWC) ."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310323"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2757667.2757679"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744876"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2345387"},{"key":"e_1_3_2_1_27_1","volume-title":"2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) .","author":"Luo Y.","unstructured":"Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch, and O. Mutlu. 2018. HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) ."},{"key":"e_1_3_2_1_28_1","volume-title":"2018 IEEE International Solid - State Circuits Conference - (ISSCC) .","author":"Maejima H.","unstructured":"H. Maejima, K. Kanda, S. Fujimura, T. Takagiwa, S. Ozawa, J. Sato, Y. Shindo, M. Sato, N. Kanagawa, J. Musha, S. Inoue, K. Sakurai, N. Morozumi, R. Fukuda, Y. Shimizu, T. Hashimoto, X. Li, Y. Shimizu, K. Abe, T. Yasufuku, T. Minamoto, H. Yoshihara, T. Yamashita, K. Satou, T. Sugimoto, F. Kono, M. Abe, T. Hashiguchi, M. Kojima, Y. Suematsu, T. Shimizu, A. Imamoto, N. Kobayashi, M. Miakashi, K. Yamaguchi, S. Bushnaq, H. Haibi, M. Ogawa, Y. Ochi, K. Kubota, T. Wakui, D. He, W. Wang, H. Minagawa, T. Nishiuchi, H. Nguyen, K. H. Kim, K. Cheah, Y. Koh, F. Lu, V. Ramachandra, S. Rajendra, S. Choi, K. Payak, N. Raghunathan, S. Georgakis, H. Sugawara, S. Lee, T. Futatsuyama, K. Hosono, N. Shibata, T. Hisada, T. Kaneko, and H. Nakamura. 2018. A 512Gb 3b\/Cell 3D flash memory on a 96-word-line-layer technology. In 2018 IEEE International Solid - State Circuits Conference - (ISSCC) ."},{"key":"e_1_3_2_1_29_1","volume-title":"Inside NAND Flash Memory","author":"Rino~Micheloni Alessia~Marelli","unstructured":"Alessia~Marelli Rino~Micheloni, Luca~Crippa. 2010. Inside NAND Flash Memory .Springer Netherlands."},{"key":"e_1_3_2_1_30_1","volume-title":"Samsung Pro 950 SSD. https:\/\/www.samsung.com\/us\/computing\/memory-storage\/solid-state-drives\/ssd-950-pro-nvme-512gb-mz-v5p512bw\/. (Aug","year":"2018","unstructured":"Samsung. 2018. Samsung Pro 950 SSD. https:\/\/www.samsung.com\/us\/computing\/memory-storage\/solid-state-drives\/ssd-950-pro-nvme-512gb-mz-v5p512bw\/. (Aug 2018)."},{"key":"e_1_3_2_1_31_1","unstructured":"Samsung. 2018. Samsung Pro 960 SSD. http:\/\/www.samsung.com\/semiconductor\/minisite\/ssd\/product\/consumer\/960pro\/. (Aug 2018)."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","unstructured":"Kshitij Sudan Niladrish Chatterjee David Nellans Manu Awasthi Rajeev Balasubramonian and Al Davis. {n. d.}. Micro-pages: Increasing DRAM Efficiency with Locality-aware Data Placement. In Proceedings of the Fifteenth Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems (ASPLOS XV). 219--230. 10.1145\/1736020.1736045","DOI":"10.1145\/1736020.1736045"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195708"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123954"},{"key":"e_1_3_2_1_35_1","volume-title":"Controlled Kernel Launch for Dynamic Parallelism in GPUs. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). 649--660","author":"Tang X.","unstructured":"X. Tang, A. Pattnaik, H. Jiang, O. Kayiran, A. Jog, S. Pai, M. Ibrahim, M. T. Kandemir, and C. R. Das. 2017. Controlled Kernel Launch for Dynamic Parallelism in GPUs. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). 649--660."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2592013"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2829974"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.5555\/2208461.2208471"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3078505.3078550"},{"key":"e_1_3_2_1_40_1","volume-title":"2017 IEEE International Solid-State Circuits Conference (ISSCC). 196--197","author":"Yamashita R.","unstructured":"R. Yamashita, S. Magia, T. Higuchi, K. Yoneya, T. Yamamura, H. Mizukoshi, S. Zaitsu, M. Yamashita, S. Toyama, N. Kamae, J. Lee, S. Chen, J. Tao, W. Mak, X. Zhang, Y. Yu, Y. Utsunomiya, Y. Kato, M. Sakai, M. Matsumoto, H. Chibvongodze, N. Ookuma, H. Yabe, S. Taigor, R. Samineni, T. Kodama, Y. Kamata, Y. Namai, J. Huynh, S. E. Wang, Y. He, T. Pham, V. Saraf, A. Petkar, M. Watanabe, K. Hayashi, P. Swarnkar, H. Miwa, A. Pradhan, S. Dey, D. Dwibedy, T. Xavier, M. Balaga, S. Agarwal, S. Kulkarni, Z. Papasaheb, S. Deora, P. Hong, M. Wei, G. Balakrishnan, T. Ariki, K. Verma, C. Siau, Y. Dong, C. H. Lu, T. Miwa, and F. Moogat. 2017. 11.1 A 512Gb 3b\/cell flash memory on 64-word-line-layer BiCS technology. In 2017 IEEE International Solid-State Circuits Conference (ISSCC). 196--197."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.5555\/3129633.3129636"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.5555\/2523721.2523761"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.5555\/3189759.3189766"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.5555\/2591272.2591298"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.5555\/2750482.2750486"}],"event":{"name":"ASPLOS '19: Architectural Support for Programming Languages and Operating Systems","location":"Providence RI USA","acronym":"ASPLOS '19","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3297858.3304035","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3297858.3304035","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3297858.3304035","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:53:14Z","timestamp":1750204394000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3297858.3304035"}},"subtitle":["Rethinking the Read Operation Granularity of 3D NAND SSDs"],"short-title":[],"issued":{"date-parts":[[2019,4,4]]},"references-count":45,"alternative-id":["10.1145\/3297858.3304035","10.1145\/3297858"],"URL":"https:\/\/doi.org\/10.1145\/3297858.3304035","relation":{},"subject":[],"published":{"date-parts":[[2019,4,4]]},"assertion":[{"value":"2019-04-04","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}