{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:29:04Z","timestamp":1750220944314,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,5,13]],"date-time":"2019-05-13T00:00:00Z","timestamp":1557705600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1527464"],"award-info":[{"award-number":["1527464"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,5,13]]},"DOI":"10.1145\/3299874.3317972","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T12:10:25Z","timestamp":1558008625000},"page":"195-200","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A Processing-In-Memory Implementation of SHA-3 Using a Voltage-Gated Spin Hall-Effect Driven MTJ-based Crossbar"],"prefix":"10.1145","author":[{"given":"Chengmo","family":"Yang","sequence":"first","affiliation":[{"name":"University of Delaware, Newark, DE, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zeyu","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Delaware, Newark, DE, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,5,13]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1038\/nature08940"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/2971808.2971907"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1039\/C6NR03169B"},{"volume-title":"Programmable spin logic based on spin hall effect in a single device,\" Advanced Electronic Materials","author":"Wan C.","key":"e_1_3_2_1_5_1","unstructured":"C. Wan, X. Zhang, Z. Yuan, C. Fang, W. Kong, Q. Zhang, H. Wu, U. Khan, and X. Han, \"Programmable spin logic based on spin hall effect in a single device,\" Advanced Electronic Materials, vol. 3, no. 3, 2017."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.4916806"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2726544"},{"key":"e_1_3_2_1_8_1","first-page":"1","article-title":"SHA-3 standard: Permutation-based hash and extendable-output functions","author":"Pritzker P.","year":"2014","unstructured":"P. Pritzker and P. Gallagher, \"SHA-3 standard: Permutation-based hash and extendable-output functions,\" Information Tech Laboratory National Institute of Standards and Technology, pp. 1--35, 2014.","journal-title":"Information Tech Laboratory National Institute of Standards and Technology"},{"key":"e_1_3_2_1_9_1","first-page":"325","volume-title":"SHA-3 implementation using ReRAM based in-memory computing architecture,\" in 18th International Symposium on Quality Electronic Design (ISQED)","author":"Bhattacharjee D.","year":"2017","unstructured":"D. Bhattacharjee, V. Pudi, and A. Chattopadhyay, \"SHA-3 implementation using ReRAM based in-memory computing architecture,\" in 18th International Symposium on Quality Electronic Design (ISQED), 2017, pp. 325--330."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/3130379.3130568"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"e_1_3_2_1_12_1","first-page":"1","volume-title":"Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs,\" in 26th International Conference on Field Programmable Logic and Applications (FPL)","author":"Winderickx J.","year":"2016","unstructured":"J. Winderickx, J. Daemen, and N. Mentens, \"Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs,\" in 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, pp. 1--4."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-27257-8_14"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"}],"event":{"name":"GLSVLSI '19: Great Lakes Symposium on VLSI 2019","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Tysons Corner VA USA","acronym":"GLSVLSI '19"},"container-title":["Proceedings of the 2019 Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299874.3317972","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3299874.3317972","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3299874.3317972","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:53:38Z","timestamp":1750204418000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299874.3317972"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5,13]]},"references-count":14,"alternative-id":["10.1145\/3299874.3317972","10.1145\/3299874"],"URL":"https:\/\/doi.org\/10.1145\/3299874.3317972","relation":{},"subject":[],"published":{"date-parts":[[2019,5,13]]},"assertion":[{"value":"2019-05-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}