{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:29:04Z","timestamp":1750220944473,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,5,13]],"date-time":"2019-05-13T00:00:00Z","timestamp":1557705600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100007140","name":"Synopsys","doi-asserted-by":"publisher","award":["Synopsys CAD Labs, IIT Kharagpur"],"award-info":[{"award-number":["Synopsys CAD Labs, IIT Kharagpur"]}],"id":[{"id":"10.13039\/100007140","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,5,13]]},"DOI":"10.1145\/3299874.3317976","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T12:10:25Z","timestamp":1558008625000},"page":"123-128","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis"],"prefix":"10.1145","author":[{"given":"Sayandeep","family":"Sanyal","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Kharagpur, Kharagpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shan Pavan Pani Krishna","family":"Garapati","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, Kharagpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amit","family":"Patra","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, Kharagpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pallab","family":"Dasgupta","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, Kharagpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mayukh","family":"Bhattacharya","sequence":"additional","affiliation":[{"name":"Synopsys Inc., San Francisco, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,5,13]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/882505.885058"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2014.6847817"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/btv428"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/191326.191529"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Nuno Guerreiro Marcelino Santos and J. P. Teixeira. 2013. Analogue and Mixed-Signal Production Test Speed-Up by Means of Fault List Compression. Vol. 04 (2013) 407--421.","DOI":"10.4236\/cs.2013.45054"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/783328.783532"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/288548.289057"},{"volume-title":"Proc. of 3rd International Conference on Electronics, Circuits, and Systems.","author":"Jurisic D.","key":"e_1_3_2_1_8_1","unstructured":"D. Jurisic, N. Mijat, and V. Cosic. 1996. Frequency Domain Approach to Fault Diagnosis of Analog Filters. In Proc. of 3rd International Conference on Electronics, Circuits, and Systems."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2016.7520721"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/368058.368426"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11760-010-0168-6"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/DCIS.2015.7388584"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.871758"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1994.292334"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.486460"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.902824"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035281"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2017.8242079"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266094"}],"event":{"name":"GLSVLSI '19: Great Lakes Symposium on VLSI 2019","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Tysons Corner VA USA","acronym":"GLSVLSI '19"},"container-title":["Proceedings of the 2019 Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299874.3317976","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3299874.3317976","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:53:38Z","timestamp":1750204418000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299874.3317976"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5,13]]},"references-count":19,"alternative-id":["10.1145\/3299874.3317976","10.1145\/3299874"],"URL":"https:\/\/doi.org\/10.1145\/3299874.3317976","relation":{},"subject":[],"published":{"date-parts":[[2019,5,13]]},"assertion":[{"value":"2019-05-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}