{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:29:04Z","timestamp":1750220944684,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,5,13]],"date-time":"2019-05-13T00:00:00Z","timestamp":1557705600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"CRISP one of six centers in JUMP an SRC program sponsored by DARPA","award":["#1730158"],"award-info":[{"award-number":["#1730158"]}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1730158","1527034"],"award-info":[{"award-number":["1730158","1527034"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,5,13]]},"DOI":"10.1145\/3299874.3318011","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T12:10:25Z","timestamp":1558008625000},"page":"255-258","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["UPIM: Unipolar Switching Logic for High Density Processing-in-Memory Applications"],"prefix":"10.1145","author":[{"given":"Joonseop","family":"Sim","sequence":"first","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}]},{"given":"Saransh","family":"Gupta","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}]},{"given":"Mohsen","family":"Imani","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}]},{"given":"Yeseong","family":"Kim","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}]},{"given":"Tajana","family":"Rosing","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2019,5,13]]},"reference":[{"key":"e_1_3_2_1_1_1","volume":"201","author":"Yang C.","unstructured":"C. Yang et al., \"Big data and cloud computing: innovation opportunities and challenges,\" International Journal of Digital Earth, 2017.","journal-title":"\"Big data and cloud computing: innovation opportunities and challenges,\" International Journal of Digital Earth"},{"key":"e_1_3_2_1_2_1","volume-title":"Silicon device scaling to the sub-10-nm regime,\" Science","author":"Ieong M.","year":"2004","unstructured":"M. Ieong et al., \"Silicon device scaling to the sub-10-nm regime,\" Science, 2004."},{"key":"e_1_3_2_1_3_1","volume-title":"A framework for collaborative learning in secure highdimensional space,\" in Cloud Computing (CLOUD)","author":"Imani M.","year":"2019","unstructured":"M. Imani et al., \"A framework for collaborative learning in secure highdimensional space,\" in Cloud Computing (CLOUD), IEEE, 2019."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1097107.1097127"},{"key":"e_1_3_2_1_5_1","volume-title":"IEEE","author":"Sim J.","year":"2018","unstructured":"J. Sim et al., \"Lupis: latch-up based ultra efficient processing in-memory system,\" in 2018 19th International Symposium on Quality Electronic Design (ISQED), IEEE, 2018."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240811"},{"key":"e_1_3_2_1_7_1","volume-title":"Rapidnn: In-memory deep neural network acceleration framework,\" arXiv preprint arXiv:1806.05794","author":"Imani M.","year":"2018","unstructured":"M. Imani et al., \"Rapidnn: In-memory deep neural network acceleration framework,\" arXiv preprint arXiv:1806.05794, 2018."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3218603.3218631"},{"key":"e_1_3_2_1_9_1","first-page":"445","volume-title":"Exploring hyperdimensional associative memory,\" in HPCA","author":"Imani M.","year":"2017","unstructured":"M. Imani et al., \"Exploring hyperdimensional associative memory,\" in HPCA, pp. 445--456, IEEE, 2017."},{"key":"e_1_3_2_1_10_1","first-page":"1","volume-title":"Nnpim: A processing in-memory architecture for neural network acceleration,\" IEEE Transactions on Computers","author":"Gupta S.","year":"2019","unstructured":"S. Gupta et al., \"Nnpim: A processing in-memory architecture for neural network acceleration,\" IEEE Transactions on Computers, pp. 1--1, 2019."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/3199700.3199704"},{"key":"e_1_3_2_1_12_1","volume-title":"IEEE","author":"Chang L.","year":"2017","unstructured":"L. Chang et al., \"Reconfigurable processing in memory architecture based on spin orbit torque,\" in 2017 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2017."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"e_1_3_2_1_14_1","first-page":"757","volume-title":"2017 22nd Asia and South Pacific","author":"Imani M.","year":"2017","unstructured":"M. Imani et al., \"Mpim: Multi-purpose in-memory processing using configurable resistive memory,\" in Design Automation Conference (ASP-DAC), 2017 22nd Asia and South Pacific, pp. 757--763, IEEE, 2017."},{"key":"e_1_3_2_1_15_1","volume":"201","author":"Kvatinsky S.","unstructured":"S. Kvatinsky et al., \"Magic: Memristor-aided logic,\" IEEE Transactions on Circuits and Systems II: Express Briefs, 2014.","journal-title":"\"Magic: Memristor-aided logic,\" IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062337"},{"key":"e_1_3_2_1_17_1","volume-title":"ACM","author":"Imani M.","year":"2019","unstructured":"M. Imani et al., \"Floatpim: In-memory acceleration of deep neural network training with high precision,\" in ISCA, ACM, 2019."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2009.5226356"},{"key":"e_1_3_2_1_19_1","volume-title":"A review of three-dimensional resistive switching cross-bar array memories from the integration and materials property points of view,\" Advanced Functional Materials","author":"Seok J. Y.","year":"2014","unstructured":"J. Y. Seok et al., \"A review of three-dimensional resistive switching cross-bar array memories from the integration and materials property points of view,\" Advanced Functional Materials, 2014."},{"key":"e_1_3_2_1_20_1","volume":"201","author":"Talati N.","unstructured":"N. Talati et al., \"Logic design within memristive memories using memristor-aided logic (magic),\" IEEE Transactions on Nanotechnology, 2016.","journal-title":"\"Logic design within memristive memories using memristor-aided logic (magic),\" IEEE Transactions on Nanotechnology"},{"key":"e_1_3_2_1_21_1","volume-title":"Resistance random access memory,\" Materials Today","author":"Chang T.-C.","year":"2016","unstructured":"T.-C. Chang et al., \"Resistance random access memory,\" Materials Today, 2016."},{"key":"e_1_3_2_1_22_1","volume-title":"2016 IFIP\/IEEE International Conference on, IEEE","author":"Amrani E.","year":"2016","unstructured":"E. Amrani et al., \"Logic design with unipolar memristors,\" in Very Large Scale Integration (VLSI-SoC), 2016 IFIP\/IEEE International Conference on, IEEE, 2016."},{"key":"e_1_3_2_1_23_1","volume":"201","author":"Kvatinsky S.","unstructured":"S. Kvatinsky et al., \"Vteam: A general model for voltage-controlled memristors,\" IEEE Transactions on Circuits and Systems II: Express Briefs, 2015.","journal-title":"\"Vteam: A general model for voltage-controlled memristors,\" IEEE Transactions on Circuits and Systems II: Express Briefs"},{"volume-title":"A complementary resistive switchbased crossbar array adder,\" IEEE journal on emerging and selected topics in circuits and systems","author":"Siemon A.","key":"e_1_3_2_1_24_1","unstructured":"A. Siemon, S. Menzel, R. Waser, and E. Linn, \"A complementary resistive switchbased crossbar array adder,\" IEEE journal on emerging and selected topics in circuits and systems, vol. 5, no. 1, pp. 64--74, 2015."},{"key":"e_1_3_2_1_25_1","volume-title":"College physics","author":"Sears F. W.","year":"1974","unstructured":"F. W. Sears et al., College physics. Addison Wesley Publishing Company, 1974."}],"event":{"name":"GLSVLSI '19: Great Lakes Symposium on VLSI 2019","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Tysons Corner VA USA","acronym":"GLSVLSI '19"},"container-title":["Proceedings of the 2019 Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299874.3318011","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3299874.3318011","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3299874.3318011","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:53:38Z","timestamp":1750204418000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299874.3318011"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5,13]]},"references-count":25,"alternative-id":["10.1145\/3299874.3318011","10.1145\/3299874"],"URL":"https:\/\/doi.org\/10.1145\/3299874.3318011","relation":{},"subject":[],"published":{"date-parts":[[2019,5,13]]},"assertion":[{"value":"2019-05-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}