{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,17]],"date-time":"2026-06-17T16:35:53Z","timestamp":1781714153939,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,5,13]],"date-time":"2019-05-13T00:00:00Z","timestamp":1557705600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"EU-H2020","award":["NeuRAM3 Cube (NEUral computing aRchitectures in Advanced Monolithic 3D-VLSI nano-technologies)"],"award-info":[{"award-number":["NeuRAM3 Cube (NEUral computing aRchitectures in Advanced Monolithic 3D-VLSI nano-technologies)"]}]},{"name":"ITEA3","award":["PARTNER (Patient-care Advancement with Responsive Technologies aNd Engagement togetheR)"],"award-info":[{"award-number":["PARTNER (Patient-care Advancement with Responsive Technologies aNd Engagement togetheR)"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,5,13]]},"DOI":"10.1145\/3299874.3319491","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T12:10:25Z","timestamp":1558008625000},"page":"495-499","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":30,"title":["Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing"],"prefix":"10.1145","author":[{"given":"Adarsha","family":"Balaji","sequence":"first","affiliation":[{"name":"Drexel University, Philadelphia, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yuefeng","family":"Wu","sequence":"additional","affiliation":[{"name":"Stichting IMEC Nederland, Eindhoven, Netherlands"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Anup","family":"Das","sequence":"additional","affiliation":[{"name":"Drexel University, Philadelphia, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Francky","family":"Catthoor","sequence":"additional","affiliation":[{"name":"IMEC Belgium & KU Leuven, Leuven, Belgium"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Siebren","family":"Schaafsma","sequence":"additional","affiliation":[{"name":"Stichting IMEC Nederland, Eindhoven, Netherlands"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,5,13]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","unstructured":"Filipp Akopyan et al. 2015. TrueNorth: Design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip. IEEE TCAD (2015).","DOI":"10.1109\/TCAD.2015.2474396"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Luca Benini and Giovanni De Micheli. 2002. Networks on chip: A new paradigm for systems on chip design. In DATE.","DOI":"10.1109\/2.976921"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","unstructured":"Kwabena A. Boahen. 1998. Communicating neuronal ensembles between neuromorphic chips. In Neuromorphic systems engineering.","DOI":"10.5555\/296556.296616"},{"key":"e_1_3_2_1_4_1","volume-title":"Noxim: An open, extensible and cycle-accurate network on chip simulator. In ASAP.","author":"Vincenzo Catania","year":"2015","unstructured":"Vincenzo Catania et al. 2015. Noxim: An open, extensible and cycle-accurate network on chip simulator. In ASAP."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","unstructured":"J. Chen et al. 1999. Segmented bus design for low-power systems. IEEE TVLSI (1999). 10.1109\/92.748197","DOI":"10.1109\/92.748197"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"T. Chou et al. 2018. CARLsim 4: An Open Source Library for Large Scale Biologically Detailed Spiking Neural Network Simulation using Heterogeneous Clusters. In IJCNN.","DOI":"10.1109\/IJCNN.2018.8489326"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"A. Das et al. 2018. Mapping of local and global synapses on spiking neuromorphic hardware. In DATE.","DOI":"10.23919\/DATE.2018.8342201"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","unstructured":"Anup Das and Akash Kumar. 2018. Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware. In GLSVLSI. 10.1145\/3194554.3194627","DOI":"10.1145\/3194554.3194627"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"P. Diehl et al. 2015. Unsupervised learning of digit recognition using spike-timing-dependent plasticity. Frontiers in computational neuroscience (2015).","DOI":"10.3389\/fncom.2015.00099"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","unstructured":"Francesco Galluppi et al. 2012. A hierachical configuration system for a massively parallel neural hardware platform. In CF. 10.1145\/2212908.2212934","DOI":"10.1145\/2212908.2212934"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","unstructured":"Yatin Hoskote et al. 2007. A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro (2007).","DOI":"10.5555\/1320302.1320837"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"Giacomo Indiveri et al. 2015. Neuromorphic architectures for spiking deep neural networks. In IEDM.","DOI":"10.1109\/IEDM.2015.7409623"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195663"},{"key":"e_1_3_2_1_14_1","unstructured":"Muhammad Mukaram Khan et al. 2008. SpiNNaker: mapping neural networks onto a massively-parallel chip multiprocessor. In IJCNN."},{"key":"e_1_3_2_1_15_1","first-page":"335","article-title":"Multi-stage interconnection network for high speed packet switching","volume":"6","year":"2002","unstructured":"Hee-choul Lee. 2002. Multi-stage interconnection network for high speed packet switching. US Patent 6,335,930.","journal-title":"US Patent"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","unstructured":"Xiaoxiao Liu et al. 2018. Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems. In ASP-DAC.","DOI":"10.5555\/3201607.3201637"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/281543.281637"},{"key":"e_1_3_2_1_18_1","volume-title":"New generation of predictive technology model for sub-45 nm early design exploration","author":"Zhao Wei","year":"2006","unstructured":"Wei Zhao and Yu Cao. 2006. New generation of predictive technology model for sub-45 nm early design exploration. IEEE TED (2006)."}],"event":{"name":"GLSVLSI '19: Great Lakes Symposium on VLSI 2019","location":"Tysons Corner VA USA","acronym":"GLSVLSI '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2019 Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299874.3319491","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3299874.3319491","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:53:38Z","timestamp":1750204418000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299874.3319491"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5,13]]},"references-count":18,"alternative-id":["10.1145\/3299874.3319491","10.1145\/3299874"],"URL":"https:\/\/doi.org\/10.1145\/3299874.3319491","relation":{},"subject":[],"published":{"date-parts":[[2019,5,13]]},"assertion":[{"value":"2019-05-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}