{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,16]],"date-time":"2026-10-16T21:20:34Z","timestamp":1792185634353,"version":"4.4.0"},"publisher-location":"New York, NY, USA","reference-count":33,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,5,13]],"date-time":"2019-05-13T00:00:00Z","timestamp":1557705600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,5,13]]},"DOI":"10.1145\/3299874.3319495","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T12:10:25Z","timestamp":1558008625000},"page":"471-476","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":38,"title":["Threats on Logic Locking"],"prefix":"10.1145","author":[{"given":"Kimia","family":"Zamiri Azar","sequence":"first","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hadi","family":"Mardani Kamali","sequence":"additional","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Avesta","family":"Sasan","sequence":"additional","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,5,13]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.24"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","unstructured":"A. Chakraborty et al. 2018. TimingSAT: timing profile embedded SAT attack. In ICCAD. 6. 10.1145\/3240765.3240857","DOI":"10.1145\/3240765.3240857"},{"key":"e_1_3_2_1_3_1","unstructured":"H. M. Kamali et al. 2018. LUT-lock: A novel LUT-based logic obfuscation for FPGA-bitstream and ASIC-hardware protection. In ISVLSI. 405--410."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"H. M. Kamali et al. 2019. Full-Lock: Hard Distributions of SAT Instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks. In DAC. 6.","DOI":"10.1145\/3316781.3317831"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","unstructured":"H. Zhou et al. 2017. CycSAT: SAT-based attack on cyclic logic encryptions. In ICCAD. 49--56.","DOI":"10.5555\/3199700.3199707"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.284"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","unstructured":"J. Rajendran et al. 2012. Security analysis of logic obfuscation. In DAC. 83--89. 10.1145\/2228360.2228377","DOI":"10.1145\/2228360.2228377"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.193"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"K. Shamsi et al. 2017. AppSAT: Approximately deobfuscating integrated circuits. In HOST. 95--100.","DOI":"10.1109\/HST.2017.7951805"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","unstructured":"K. Shamsi et al. 2017. Cyclic obfuscation for creating sat-unresolvable circuits. In GLSVLSI. 173--178. 10.1145\/3060403.3060458","DOI":"10.1145\/3060403.3060458"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","unstructured":"K. Shamsi et al. 2018. Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures. In GLSVLSI. 147--152. 10.1145\/3194554.3194580","DOI":"10.1145\/3194554.3194580"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"K. Z. Azar et al. 2019. SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks. IACR Trans. on CHES (TCHES) (2019) 97--122.","DOI":"10.46586\/tches.v2019.i1.97-122"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","unstructured":"M. Li et al. 2017. Provably secure camouflaging strategy for IC protection. IEEE Trans. on CAD (TCAD) (2017). 10.1145\/2966986.2967065","DOI":"10.1145\/2966986.2967065"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2335155"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"M. Yasin et al. 2016. SARLock: SAT Attack Resistant Logic Locking. In HOST. 236--241.","DOI":"10.1109\/HST.2016.7495588"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","unstructured":"M. Yasin et. al. 2017. Provably-secure logic locking: From theory to practice. In ACM-CCS. 1601--1618. 10.1145\/3133956.3133985","DOI":"10.1145\/3133956.3133985"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2017.2740364"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"M. Yasin et al. 2017. Security analysis of anti-sat. In ASP-DAC. 342--347.","DOI":"10.1109\/ASPDAC.2017.7858346"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","unstructured":"M. Yasin et al. 2017. What to lock? Functional and parametric locking. In GLSVLSI. 351--356. 10.1145\/3060403.3060492","DOI":"10.1145\/3060403.3060492"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"crossref","unstructured":"P. Subramanyan et al. 2015. Evaluating the security of logic encryption algorithms. In HOST. 137--143.","DOI":"10.1109\/HST.2015.7140252"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","unstructured":"P. Tuyls et al. 2006. Read-proof hardware from protective coatings. In CHES. 369--383. 10.1007\/11894063_29","DOI":"10.1007\/11894063_29"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","unstructured":"S. Roshanisefat et al. 2018. Benchmarking the capabilities and limitations of SAT solvers in defeating obfuscation schemes. In IOLTS. 275--280.","DOI":"10.1109\/IOLTS.2018.8474189"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","unstructured":"S. Roshanisefat et al. 2018. SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware. In GLSVLSI. 153--158. 10.1145\/3194554.3194596","DOI":"10.1145\/3194554.3194596"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","unstructured":"T. Winograd et al. 2016. Hybrid STT-CMOS designs for reverse-engineering prevention. In DAC. 6. 10.1145\/2897937.2898099","DOI":"10.1145\/2897937.2898099"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"crossref","unstructured":"X. Xu et al. 2017. Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks. In CHES. 189--210.","DOI":"10.1007\/978-3-319-66787-4_10"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"crossref","unstructured":"Y. Shen et al. 2018. SAT-based bit-flipping attack on logic encryptions. In DATE. 629--632.","DOI":"10.23919\/DATE.2018.8342086"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","unstructured":"Y. Shen et al. 2019. BeSAT: behavioral SAT-based attack on cyclic logic encryption. In ASP-DAC. ACM 657--662. 10.1145\/3287624.3287670","DOI":"10.1145\/3287624.3287670"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","unstructured":"Y. Xie et al. 2017. Delay locking: Security enhancement of logic locking against ic counterfeiting and overproduction. In DAC. 9. 10.1145\/3061639.3062226","DOI":"10.1145\/3061639.3062226"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2404876"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","unstructured":"Y. Shen and H. Zhou. 2017. Double dip: Re-evaluating security of logic encryption algorithms. In GLSVLSI. 179--184. 10.1145\/3060403.3060469","DOI":"10.1145\/3060403.3060469"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"crossref","unstructured":"D. Sirone and P. Subramanyan. 2018. Functional Analysis Attacks on Logic Locking. arXiv preprint arXiv:1811.12088 (2018).","DOI":"10.23919\/DATE.2019.8715163"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"crossref","unstructured":"Y. Xie and A. Srivastava. 2016. Mitigating sat attack on logic locking. In CHES. 127--146.","DOI":"10.1007\/978-3-662-53140-2_7"},{"key":"e_1_3_2_1_33_1","volume-title":"yeh","author":"A.","year":"2012","unstructured":"A. yeh. 2012. Trends in the global IC design service market. DIGITIMES research (2012)."}],"event":{"name":"GLSVLSI '19: Great Lakes Symposium on VLSI 2019","location":"Tysons Corner VA USA","acronym":"GLSVLSI '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2019 Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299874.3319495","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3299874.3319495","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:53:38Z","timestamp":1750204418000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299874.3319495"}},"subtitle":["A Decade Later"],"short-title":[],"issued":{"date-parts":[[2019,5,13]]},"references-count":33,"alternative-id":["10.1145\/3299874.3319495","10.1145\/3299874"],"URL":"https:\/\/doi.org\/10.1145\/3299874.3319495","relation":{},"subject":[],"published":{"date-parts":[[2019,5,13]]},"assertion":[{"value":"2019-05-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}