{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:29:05Z","timestamp":1750220945613,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,4,4]],"date-time":"2019-04-04T00:00:00Z","timestamp":1554336000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100007140","name":"Synopsys","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007140","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004368","name":"Taiwan Semiconductor Manufacturing Company","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004368","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,4,4]]},"DOI":"10.1145\/3299902.3309755","type":"proceedings-article","created":{"date-parts":[[2019,4,10]],"date-time":"2019-04-10T19:07:28Z","timestamp":1554923248000},"page":"93-100","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement"],"prefix":"10.1145","author":[{"given":"Hua-Yu","family":"Chang","sequence":"first","affiliation":[{"name":"Synopsys, Inc., Taipei, Taiwan Roc"}]},{"given":"Iris Hui-Ru","family":"Jiang","sequence":"additional","affiliation":[{"name":"National Taiwan University, Taipei, Taiwan Roc"}]}],"member":"320","published-online":{"date-parts":[[2019,4,4]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"D. Abercrombie. 2017. Will EUV kill multi-patterning? (January 2017). Semiconductor Engineering. Retrieved from https:\/\/semiengineering.com\/will-euv-kill-multi-patterning\/ D. Abercrombie. 2017. Will EUV kill multi-patterning? (January 2017). Semiconductor Engineering. Retrieved from https:\/\/semiengineering.com\/will-euv-kill-multi-patterning\/"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1515\/aot-2015-0036","article-title":"ITRS lithography roadmap: 2015 challenges","volume":"4","author":"Neisser M.","year":"2015","journal-title":"Adv. Opt. Techn."},{"key":"e_1_3_2_1_3_1","unstructured":"M. van den Brink. 2014. Many ways to shrink: the right moves to 10 nanometer and beyond. (November 2014). Retrieved from https:\/\/staticwww.asml.com\/doclib\/investor\/asml_3_Investor_Day-Many_ways_to_shrink_MvdBrink1.pdf M. van den Brink. 2014. Many ways to shrink: the right moves to 10 nanometer and beyond. (November 2014). Retrieved from https:\/\/staticwww.asml.com\/doclib\/investor\/asml_3_Investor_Day-Many_ways_to_shrink_MvdBrink1.pdf"},{"volume-title":"Proc. SPIE 9427","year":"2015","author":"Badr Y.","key":"e_1_3_2_1_4_1"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2512903"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488818"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2288678"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2387840"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593152"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2681068"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2232710"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742881"},{"key":"e_1_3_2_1_13_1","unstructured":"J. Dorsc. 2015. Changes and challenges abound in multi-patterning lithography. (February 2015). Semiconductor Manufacturing and Design (SemiMD). Retrieved from http:\/\/www.semi.org\/en\/node\/54491 J. Dorsc. 2015. Changes and challenges abound in multi-patterning lithography. (February 2015). Semiconductor Manufacturing and Design (SemiMD). Retrieved from http:\/\/www.semi.org\/en\/node\/54491"},{"key":"e_1_3_2_1_14_1","unstructured":"M. White. 2014. A look behind the mask of multi-patterning. (October 2014) Electronic Design. Retrieved from http:\/\/www.electronicdesign.com\/eda\/look-behind-mask-multi-patterning M. White. 2014. A look behind the mask of multi-patterning. (October 2014) Electronic Design. Retrieved from http:\/\/www.electronicdesign.com\/eda\/look-behind-mask-multi-patterning"},{"volume-title":"Proc. SPIE 9235","year":"2014","author":"Yu B.","key":"e_1_3_2_1_15_1"},{"key":"e_1_3_2_1_16_1","unstructured":"D. Payne. 2014. Design rule checking (DRC) meets new challenges. (December 2014). SemiWiki. Retrieved from https:\/\/www.semiwiki.com\/forum\/content\/4062-design-rule-checking-drc-meets-new-challenges.html D. Payne. 2014. Design rule checking (DRC) meets new challenges. (December 2014). SemiWiki. Retrieved from https:\/\/www.semiwiki.com\/forum\/content\/4062-design-rule-checking-drc-meets-new-challenges.html"},{"key":"e_1_3_2_1_17_1","unstructured":"E. Sperling. 2018. Design rule complexity rising. (April 2018). Manufacturing & Process Technology Semiconductor Engineering. Retrieved from https:\/\/semiengineering.com\/design-rule-complexity-rising\/ E. Sperling. 2018. Design rule complexity rising. (April 2018). Manufacturing & Process Technology Semiconductor Engineering. Retrieved from https:\/\/semiengineering.com\/design-rule-complexity-rising\/"},{"key":"e_1_3_2_1_18_1","unstructured":"D.E. Knuth. 2000. Dancing links. arXiv:cs\/0011047. Retrieved from https:\/\/arxiv.org\/abs\/cs\/0011047 D.E. Knuth. 2000. Dancing links. arXiv:cs\/0011047. Retrieved from https:\/\/arxiv.org\/abs\/cs\/0011047"},{"key":"e_1_3_2_1_19_1","unstructured":"Gurobi Optimization Inc. 2014. Gurobi Optimizer 7.5.1. Gurobi Optimization Inc. 2014. Gurobi Optimizer 7.5.1."}],"event":{"name":"ISPD '19: International Symposium on Physical Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"San Francisco CA USA","acronym":"ISPD '19"},"container-title":["Proceedings of the 2019 International Symposium on Physical Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299902.3309755","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3299902.3309755","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:53:39Z","timestamp":1750204419000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3299902.3309755"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4,4]]},"references-count":19,"alternative-id":["10.1145\/3299902.3309755","10.1145\/3299902"],"URL":"https:\/\/doi.org\/10.1145\/3299902.3309755","relation":{},"subject":[],"published":{"date-parts":[[2019,4,4]]},"assertion":[{"value":"2019-04-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}