{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,20]],"date-time":"2026-10-20T11:20:25Z","timestamp":1792495225026,"version":"4.5.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2019,3,18]],"date-time":"2019-03-18T00:00:00Z","timestamp":1552867200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Singapore Ministry of Education Academic Research Fund","award":["Tier 2 MOE2015-T2-2-088"],"award-info":[{"award-number":["Tier 2 MOE2015-T2-2-088"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2019,3,31]]},"abstract":"<jats:p>\n            Convolutional Neural Networks (CNN) have been widely deployed in diverse application domains. There has been significant progress in accelerating both their training and inference using high-performance GPUs, FPGAs, and custom ASICs for datacenter-scale environments. The recent proliferation of mobile and Internet of Things (IoT) devices have necessitated real-time, energy-efficient deep neural network inference on embedded-class, resource-constrained platforms. In this context, we present\n            <jats:italic>Synergy<\/jats:italic>\n            , an automated, hardware-software co-designed, pipelined, high-throughput CNN inference framework on embedded heterogeneous system-on-chip (SoC) architectures (Xilinx Zynq).\n            <jats:italic>Synergy<\/jats:italic>\n            leverages, through multi-threading, all the available on-chip resources, which includes the dual-core ARM processor along with the FPGA and the NEON Single-Instruction Multiple-Data (SIMD) engines as accelerators. Moreover,\n            <jats:italic>Synergy<\/jats:italic>\n            provides a unified abstraction of the heterogeneous accelerators (FPGA and NEON) and can adapt to different network configurations at runtime without changing the underlying hardware accelerator architecture by balancing workload across accelerators through work-stealing.\n            <jats:italic>Synergy<\/jats:italic>\n            achieves 7.3X speedup, averaged across seven CNN models, over a well-optimized software-only solution.\n            <jats:italic>Synergy<\/jats:italic>\n            demonstrates substantially better throughput and energy-efficiency compared to the contemporary CNN implementations on the same SoC architecture.\n          <\/jats:p>","DOI":"10.1145\/3301278","type":"journal-article","created":{"date-parts":[[2019,3,18]],"date-time":"2019-03-18T12:09:30Z","timestamp":1552910970000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":36,"title":["Synergy"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0746-2921","authenticated-orcid":false,"given":"Guanwen","family":"Zhong","sequence":"first","affiliation":[{"name":"National University of Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Akshat","family":"Dubey","sequence":"additional","affiliation":[{"name":"National University of Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Cheng","family":"Tan","sequence":"additional","affiliation":[{"name":"National University of Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tulika","family":"Mitra","sequence":"additional","affiliation":[{"name":"National University of Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,3,18]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ARM Infocenter. 2018. Retrieved from http:\/\/infocenter.arm.com.  ARM Infocenter. 2018. Retrieved from http:\/\/infocenter.arm.com."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2016.2545298"},{"key":"e_1_2_1_3_1","volume-title":"2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 152--159","author":"Guan Y.","unstructured":"Y. Guan , H. Liang , N. Xu , W. Wang , S. Shi , X. Chen , G. Sun , W. Zhang , and J. Cong . 2017. FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates . In 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 152--159 . Y. Guan, H. Liang, N. Xu, W. Wang, S. Shi, X. Chen, G. Sun, W. Zhang, and J. Cong. 2017. FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates. In 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 152--159."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2705069"},{"key":"e_1_2_1_5_1","volume-title":"Automation Test in Europe Conference Exhibition (DATE)","author":"Hashemi S.","year":"2017","unstructured":"S. Hashemi , N. Anthony , H. Tann , R. I. Bahar , and S. Reda . 2017. Understanding the impact of precision quantization on the accuracy and energy of neural networks. In Design , Automation Test in Europe Conference Exhibition (DATE) , 2017 . 1474--1479. S. Hashemi, N. Anthony, H. Tann, R. I. Bahar, and S. Reda. 2017. Understanding the impact of precision quantization on the accuracy and energy of neural networks. In Design, Automation Test in Europe Conference Exhibition (DATE), 2017. 1474--1479."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2968455.2968511"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2647868.2654889"},{"key":"e_1_2_1_8_1","volume-title":"2017 30th IEEE International System-on-Chip Conference (SOCC). 268--273","author":"Kim J. H.","unstructured":"J. H. Kim , B. Grady , R. Lian , J. Brothers , and J. H. Anderson . 2017. FPGA-based CNN inference accelerator synthesized from multi-threaded C software . In 2017 30th IEEE International System-on-Chip Conference (SOCC). 268--273 . J. H. Kim, B. Grady, R. Lian, J. Brothers, and J. H. Anderson. 2017. FPGA-based CNN inference accelerator synthesized from multi-threaded C software. In 2017 30th IEEE International System-on-Chip Conference (SOCC). 268--273."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1596532.1596540"},{"key":"e_1_2_1_11_1","volume-title":"2011 IEEE International Conference on Signal and Image Processing Applications (ICSIPA). 342--347","author":"Nagi J.","unstructured":"J. Nagi , F. Ducatelle , G. A. Di Caro , D. Cire\u015fan , U. Meier , A. Giusti , F. Nagi , J. Schmidhuber , and L. M. Gambardella . 2011. Max-pooling convolutional neural networks for vision-based hand gesture recognition . In 2011 IEEE International Conference on Signal and Image Processing Applications (ICSIPA). 342--347 . J. Nagi, F. Ducatelle, G. A. Di Caro, D. Cire\u015fan, U. Meier, A. Giusti, F. Nagi, J. Schmidhuber, and L. M. Gambardella. 2011. Max-pooling convolutional neural networks for vision-based hand gesture recognition. In 2011 IEEE International Conference on Signal and Image Processing Applications (ICSIPA). 342--347."},{"key":"e_1_2_1_12_1","volume-title":"NIPS Workshop on Deep Learning and Unsupervised Feature Learning.","author":"Netzer Yuval","unstructured":"Yuval Netzer , Tao Wang , Adam Coates , Alessandro Bissacco , Bo Wu , and Andrew Y. Ng . 2011. Reading digits in natural images with unsupervised feature learning . In NIPS Workshop on Deep Learning and Unsupervised Feature Learning. Yuval Netzer, Tao Wang, Adam Coates, Alessandro Bissacco, Bo Wu, and Andrew Y. Ng. 2011. Reading digits in natural images with unsupervised feature learning. In NIPS Workshop on Deep Learning and Unsupervised Feature Learning."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"e_1_2_1_14_1","volume-title":"Darknet: Open Source Neural Networks in C. Retrieved","author":"Redmon Joseph","year":"2018","unstructured":"Joseph Redmon . 2018 . Darknet: Open Source Neural Networks in C. Retrieved February 8, 2018 from https:\/\/pjreddie.com\/darknet. Joseph Redmon. 2018. Darknet: Open Source Neural Networks in C. Retrieved February 8, 2018 from https:\/\/pjreddie.com\/darknet."},{"key":"e_1_2_1_15_1","unstructured":"Christoph R\u00fcthing et al. 2016. Self-adaptation in programmable automation controllers based on hybrid multi-cores. Master Thesis University of Paderborn (2016).  Christoph R\u00fcthing et al. 2016. Self-adaptation in programmable automation controllers based on hybrid multi-cores. Master Thesis University of Paderborn (2016)."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080221"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847276"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"key":"e_1_2_1_19_1","volume-title":"2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 40--47","author":"Venieris S. I.","unstructured":"S. I. Venieris and C. S. Bouganis . 2016. fpgaConvNet: A framework for mapping convolutional neural networks on FPGAs . In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 40--47 . S. I. Venieris and C. S. Bouganis. 2016. fpgaConvNet: A framework for mapping convolutional neural networks on FPGAs. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 40--47."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021791"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898003"},{"key":"e_1_2_1_22_1","unstructured":"Xilinx Inc. 2018. Retrieved from http:\/\/www.xilinx.com.  Xilinx Inc. 2018. Retrieved from http:\/\/www.xilinx.com."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967011"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934644"},{"key":"e_1_2_1_26_1","volume-title":"Automation Test in Europe Conference Exhibition (DATE). 1141--1146","author":"Zhong G.","unstructured":"G. Zhong , A. Prakash , S. Wang , Y. Liang , T. Mitra , and S. Niar . 2017. Design space exploration of FPGA-based accelerators with multi-level parallelism. In Design , Automation Test in Europe Conference Exhibition (DATE). 1141--1146 . G. Zhong, A. Prakash, S. Wang, Y. Liang, T. Mitra, and S. Niar. 2017. Design space exploration of FPGA-based accelerators with multi-level parallelism. In Design, Automation Test in Europe Conference Exhibition (DATE). 1141--1146."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3301278","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3301278","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T00:58:02Z","timestamp":1750208282000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3301278"}},"subtitle":["An HW\/SW Framework for High Throughput CNNs on Embedded Heterogeneous SoC"],"short-title":[],"issued":{"date-parts":[[2019,3,18]]},"references-count":26,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2019,3,31]]}},"alternative-id":["10.1145\/3301278"],"URL":"https:\/\/doi.org\/10.1145\/3301278","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,3,18]]},"assertion":[{"value":"2018-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-03-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}