{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T15:56:32Z","timestamp":1781193392761,"version":"3.54.1"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2019,1,30]],"date-time":"2019-01-30T00:00:00Z","timestamp":1548806400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"NSERC\/Intel Industrial Research Chair in Programmable Silicon"},{"name":"Huawei"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2019,3,31]]},"abstract":"<jats:p>FPGAs are becoming more heteregeneous to better adapt to different markets, motivating rapid exploration of different blocks\/tiles for FPGAs. To evaluate a new FPGA architectural idea, one should be able to accurately obtain the area, delay, and energy consumption of the block of interest. However, current FPGA circuit design tools can only model simple, homogeneous FPGA architectures with basic logic blocks and also lack DSP and other heterogeneous block support. Modern FPGAs are instead composed of many different tiles, some of which are designed in a full custom style and some of which mix standard cell and full custom styles.<\/jats:p>\n          <jats:p>To fill this modelling gap, we introduce COFFE 2, an open-source FPGA design toolset for automatic FPGA circuit design. COFFE 2 uses a mix of full custom and standard cell flows and supports not only complex logic blocks with fracturable lookup tables and hard arithmetic but also arbitrary heterogeneous blocks. To validate COFFE 2 and demonstrate its features, we design and evaluate a multi-mode Stratix III-like DSP block and several logic tiles with fracturable LUTs and hard arithmetic. We also demonstrate how COFFE 2\u2019s interface to VTR allows full evaluation of block-routing interfaces and various fracturable 6-LUT architectures.<\/jats:p>","DOI":"10.1145\/3301298","type":"journal-article","created":{"date-parts":[[2019,1,30]],"date-time":"2019-01-30T12:58:34Z","timestamp":1548853114000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":61,"title":["COFFE 2"],"prefix":"10.1145","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1044-4460","authenticated-orcid":false,"given":"Sadegh","family":"Yazdanshenas","sequence":"first","affiliation":[{"name":"University of Toronto, Toronto, Ontario, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vaughn","family":"Betz","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, Ontario, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,1,30]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Predictive Technology Model. 2018. Retrieved from http:\/\/ptm.asu.edu\/.  Predictive Technology Model. 2018. Retrieved from http:\/\/ptm.asu.edu\/."},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the International Conference on Field-Programmable Technology (FPT\u201912)","author":"Mohamed","unstructured":"Mohamed S. Abdelfattah and Vaughn Betz. 2012. Design tradeoffs for hard and soft FPGA-based networks-on-chip . In Proceedings of the International Conference on Field-Programmable Technology (FPT\u201912) . 95--103. Mohamed S. Abdelfattah and Vaughn Betz. 2012. Design tradeoffs for hard and soft FPGA-based networks-on-chip. In Proceedings of the International Conference on Field-Programmable Technology (FPT\u201912). 95--103."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2015.7293953"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606687"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00014"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"e_1_2_1_8_1","volume-title":"Optimization and Modeling of FPGA Circuitry in Advanced Process Technology. Master\u2019s thesis","author":"Chiasson Charles","unstructured":"Charles Chiasson . 2013. Optimization and Modeling of FPGA Circuitry in Advanced Process Technology. Master\u2019s thesis . University of Toronto . Charles Chiasson. 2013. Optimization and Modeling of FPGA Circuitry in Advanced Process Technology. Master\u2019s thesis. University of Toronto."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718327"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP\u201917)","author":"Alexander S.","unstructured":"S. Alexander Chin et al. 2017. CGRA-ME: A unified framework for CGRA modelling and exploration . In Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP\u201917) . 184--189. S. Alexander Chin et al. 2017. CGRA-ME: A unified framework for CGRA modelling and exploration. In Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP\u201917). 184--189."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174272"},{"key":"e_1_2_1_12_1","volume-title":"Dunlop","author":"Fishburn John P.","year":"1985","unstructured":"John P. Fishburn and Alfred E . Dunlop . 1985 . TILOS : A posynomial programming approach to transistor sizing. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201985). Springer , 326--328. John P. Fishburn and Alfred E. Dunlop. 1985. TILOS: A posynomial programming approach to transistor sizing. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201985). Springer, 326--328."},{"key":"e_1_2_1_13_1","unstructured":"Intel Corporation. 2017. Stratix 10 GX\/SX device overview. Retrieved from https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/hb\/stratix-10\/s10-overview.pdf.  Intel Corporation. 2017. Stratix 10 GX\/SX device overview. Retrieved from https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/hb\/stratix-10\/s10-overview.pdf."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.31"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL\u201915)","author":"Kim Jin Hee","unstructured":"Jin Hee Kim and Jason H. Anderson . 2015. Synthesizable FPGA fabrics targetable by the verilog-to-routing (VTR) CAD flow . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL\u201915) . 1--8. Jin Hee Kim and Jason H. Anderson. 2015. Synthesizable FPGA fabrics targetable by the verilog-to-routing (VTR) CAD flow. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL\u201915). 1--8."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2031318"},{"key":"e_1_2_1_17_1","unstructured":"Lattice Semiconductor Corporation. 2016. CrossLink I2C hardened IP usage guide. Retrieved from https:\/\/www.latticesemi.com\/Products\/FPGAandCPLD\/CrossLink.  Lattice Semiconductor Corporation. 2016. CrossLink I2C hardened IP usage guide. Retrieved from https:\/\/www.latticesemi.com\/Products\/FPGAandCPLD\/CrossLink."},{"key":"e_1_2_1_18_1","unstructured":"Lattice Semiconductor Corporation. 2016. Power management and calculation for CrossLink devices. Retrieved from https:\/\/www.latticesemi.com\/Products\/FPGAandCPLD\/CrossLink.  Lattice Semiconductor Corporation. 2016. Power management and calculation for CrossLink devices. Retrieved from https:\/\/www.latticesemi.com\/Products\/FPGAandCPLD\/CrossLink."},{"key":"e_1_2_1_19_1","unstructured":"David Lewis et al. 2005. Fracturable lookup table and logic element. U.S. Patent 6943580.  David Lewis et al. 2005. Fracturable lookup table and logic element. U.S. Patent 6943580."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435292"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046195"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/2650280.2650384"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645503"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689076"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2016.7929181"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.4870917"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216924"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950419"},{"key":"e_1_2_1_30_1","unstructured":"Xilinx Corporation. 2015. Virtex-5 family overview. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds100.pdf.  Xilinx Corporation. 2015. Virtex-5 family overview. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds100.pdf."},{"key":"e_1_2_1_31_1","unstructured":"Xilinx Corporation. 2016. UltraScale architecture and product overview. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds890-ultrascale-overview.pdf.  Xilinx Corporation. 2016. UltraScale architecture and product overview. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds890-ultrascale-overview.pdf."},{"key":"e_1_2_1_32_1","unstructured":"Xilinx Corporation. 2017. Zynq UltraScale+ RFSoC data sheet: Overview. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds889-zynq-usp-rfsoc-overview.pdf.  Xilinx Corporation. 2017. Zynq UltraScale+ RFSoC data sheet: Overview. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds889-zynq-usp-rfsoc-overview.pdf."},{"key":"e_1_2_1_33_1","unstructured":"Xilinx Corporation. 2018. Xilinx Unveils Revolutionary Adaptable Computing Product Category. Retrieved from https:\/\/www.xilinx.com\/news\/press\/2018\/xilinx-unveils-revolutionary-adaptable-computing-product-category.html.  Xilinx Corporation. 2018. Xilinx Unveils Revolutionary Adaptable Computing Product Category. Retrieved from https:\/\/www.xilinx.com\/news\/press\/2018\/xilinx-unveils-revolutionary-adaptable-computing-product-category.html."},{"key":"e_1_2_1_34_1","unstructured":"Saeyang Yang. 1991. Logic Synthesis and Optimization Benchmarks User Guide: Version 3.0. MCNC.  Saeyang Yang. 1991. Logic Synthesis and Optimization Benchmarks User Guide: Version 3.0. MCNC."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021731"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2017.8280115"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056807"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847280"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2016.7929528"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056826"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3301298","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3301298","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:02:04Z","timestamp":1750208524000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3301298"}},"subtitle":["Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures"],"short-title":[],"issued":{"date-parts":[[2019,1,30]]},"references-count":40,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2019,3,31]]}},"alternative-id":["10.1145\/3301298"],"URL":"https:\/\/doi.org\/10.1145\/3301298","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,1,30]]},"assertion":[{"value":"2018-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-01-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}