{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:24:27Z","timestamp":1773192267665,"version":"3.50.1"},"reference-count":38,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2019,3,18]],"date-time":"2019-03-18T00:00:00Z","timestamp":1552867200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2019,3,31]]},"abstract":"<jats:p>With the popularity of modern FPGAs, the business of FPGA specific intellectual properties (IP) is expanding rapidly. This also brings in the concern of IP protection. FPGA vendors are making serious efforts toward IP protection, leading to standardization schemes like IEEE P1735. However, efficient techniques to prevent unauthorized overuse of IP still remain an open question. In this article, we propose a two-party IP protection scheme combining the re-configurable look-up table primitive of modern FPGAs with physically unclonable functions (PUF). The proposed scheme works with the assumption that the FPGA vendor provides the assurance of confidentiality and integrity of the developed IP. The proposed scheme is considerably lightweight compared to existing schemes, prevents overuse, and does not involve FPGA vendors or trusted third parties for IP licensing. The validation of the proposed scheme is done on MCNC\u201991 benchmark and third-party IPs like AES and lightweight MIPS processors.<\/jats:p>","DOI":"10.1145\/3301307","type":"journal-article","created":{"date-parts":[[2019,3,18]],"date-time":"2019-03-18T12:09:30Z","timestamp":1552910970000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Combining PUF with RLUTs"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4664-5237","authenticated-orcid":false,"given":"Debapriya Basu","family":"Roy","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Kharagpur, India"}]},{"given":"Shivam","family":"Bhasin","sequence":"additional","affiliation":[{"name":"Temasek Laboratories, Nanyang Technological University, Singapore"}]},{"given":"Ivica","family":"Nikoli\u0107","sequence":"additional","affiliation":[{"name":"National University of Singapore, Singapore"}]},{"given":"Debdeep","family":"Mukhopadhyay","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, India"}]}],"member":"320","published-online":{"date-parts":[[2019,3,18]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP)","year":"2014","unstructured":"2014. IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) . IEEE SA-1735- 2014 . Retrieved from https:\/\/standards.ieee.org\/findstds\/standard\/1735-2014.html. 2014. IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP). IEEE SA-1735-2014. Retrieved from https:\/\/standards.ieee.org\/findstds\/standard\/1735-2014.html."},{"key":"e_1_2_1_2_1","volume-title":"IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP)","year":"2014","unstructured":"2015. IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) . IEEE Std 1735- 2014 (Incorporates IEEE Std 1735-2014\/Cor 1-2015), 1--90. 2015. IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP). IEEE Std 1735-2014 (Incorporates IEEE Std 1735-2014\/Cor 1-2015), 1--90."},{"key":"e_1_2_1_3_1","unstructured":"Actel. 2003. Implementation of Security in Actel\u2019s ProASIC and ProASICPLUS Flash-Based FPGAs. Retrieved from http:\/\/www.actel.com\/documents\/Flash_Security_AN.pdf.  Actel. 2003. Implementation of Security in Actel\u2019s ProASIC and ProASIC PLUS Flash-Based FPGAs. Retrieved from http:\/\/www.actel.com\/documents\/Flash_Security_AN.pdf."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450129"},{"key":"e_1_2_1_6_1","volume-title":"Debapriya Basu Roy, and Debdeep Mukhopadhyay","author":"Bag Arnab","year":"2018","unstructured":"Arnab Bag , Sikhar Patranabis , Debapriya Basu Roy, and Debdeep Mukhopadhyay . 2018 . Cryptographically secure multi-tenant provisioning of FPGAs . arXiv preprint arXiv:1802.04136 (2018). https:\/\/arxiv.org\/abs\/1802.04136 Arnab Bag, Sikhar Patranabis, Debapriya Basu Roy, and Debdeep Mukhopadhyay. 2018. Cryptographically secure multi-tenant provisioning of FPGAs. arXiv preprint arXiv:1802.04136 (2018). https:\/\/arxiv.org\/abs\/1802.04136"},{"key":"e_1_2_1_7_1","volume-title":"Secure System Design and Trustable Computing","author":"Soudan Bassel","unstructured":"Bassel Soudan , Wael Adi , and Abdulrahman Hanoun . 2016. IP protection of FPGA cores through a novel public\/secret-key encryption mechanism . In Secure System Design and Trustable Computing . Springer , 369\u2013389. Bassel Soudan, Wael Adi, and Abdulrahman Hanoun. 2016. IP protection of FPGA cores through a novel public\/secret-key encryption mechanism. In Secure System Design and Trustable Computing. Springer, 369\u2013389."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2016.2553454"},{"key":"e_1_2_1_10_1","volume-title":"Retrieved","author":"Oto Petura Lilian Bossuet Marek Laban","year":"2017","unstructured":"Marek Laban Oto Petura Lilian Bossuet Viktor Fischer Brice Colombier , Ugo Mureddu . 2017 . Complete activation scheme for IP design protection . Retrieved March 11, 2018 from http:\/\/www.hostsymposium.org\/host2017\/hwdemo\/HOST_2017_hwdemo_3.pdf. Marek Laban Oto Petura Lilian Bossuet Viktor Fischer Brice Colombier, Ugo Mureddu. 2017. Complete activation scheme for IP design protection. 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