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Syst."],"published-print":{"date-parts":[[2019,3,31]]},"abstract":"<jats:p>\n            The coming era of\n            <jats:italic>big data<\/jats:italic>\n            revives the Processing-in-memory (PIM) architecture to relieve the\n            <jats:italic>memory wall<\/jats:italic>\n            problem that embarrasses the modern computing system. However, most existing PIM designs just put computing units closer to memory, rather than a complete integration of them due to their incompatibility in CMOS manufacturing. Fortunately, the emerging Resistive-RAM (ReRAM) offers new hope to this dilemma owing to its inherent memory and computing capability using the same device. In this article, we propose a ReRAM memory structure with efficient PIM capability of both logic and add operations. It first leverages non-linearity to suppress\n            <jats:italic>sneak current<\/jats:italic>\n            and thus sustains high memory density. Using a differential bit cell, it also enables efficient processing of arbitrary logic functions using the same memory cells with non-destructive operations. Then, a novel PIM adder is proposed, which customizes a sneak current path as the carry-chain for fast carry propagation and improves adder performance significantly. In the experiment, the proposed PIM demonstrates higher efficiency in both computing area and performance for logic and addition, which greatly increases the ReRAM PIM applicability for future computable architectures.\n          <\/jats:p>","DOI":"10.1145\/3306495","type":"journal-article","created":{"date-parts":[[2019,3,22]],"date-time":"2019-03-22T13:09:51Z","timestamp":1553260191000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations"],"prefix":"10.1145","volume":"24","author":[{"given":"Taozhong","family":"Li","sequence":"first","affiliation":[{"name":"Shanghai Jiao Tong University, China"}]},{"given":"Qin","family":"Wang","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, China"}]},{"given":"Yongxin","family":"Zhu","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences, China"}]},{"given":"Jianfei","family":"Jiang","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, China"}]},{"given":"Guanghui","family":"He","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, China"}]},{"given":"Jing","family":"Jin","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, China"}]},{"given":"Zhigang","family":"Mao","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, China"}]},{"given":"Naifeng","family":"Jing","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University"}]}],"member":"320","published-online":{"date-parts":[[2019,3,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750385"},{"key":"e_1_2_1_2_1","volume-title":"Memristive switches enable stateful logic operations via material implication. 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