{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,14]],"date-time":"2026-03-14T17:58:13Z","timestamp":1773511093302,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":111,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,22]],"date-time":"2019-06-22T00:00:00Z","timestamp":1561161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,22]]},"DOI":"10.1145\/3307650.3322206","type":"proceedings-article","created":{"date-parts":[[2019,6,14]],"date-time":"2019-06-14T12:42:33Z","timestamp":1560516153000},"page":"143-156","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":41,"title":["Janus"],"prefix":"10.1145","author":[{"given":"Sihang","family":"Liu","sequence":"first","affiliation":[{"name":"University of Virginia"}]},{"given":"Korakit","family":"Seemakhupt","sequence":"additional","affiliation":[{"name":"University of Virginia"}]},{"given":"Gennady","family":"Pekhimenko","sequence":"additional","affiliation":[{"name":"University of Toronto"}]},{"given":"Aasheesh","family":"Kolli","sequence":"additional","affiliation":[{"name":"Penn State University and VMware Research"}]},{"given":"Samira","family":"Khan","sequence":"additional","affiliation":[{"name":"University of Virginia"}]}],"member":"320","published-online":{"date-parts":[[2019,6,22]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.452.0287"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006719"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/3035918.3054780"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2723372.2749441"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_7_1","volume-title":"Armv8-A architecture evolution. https:\/\/community.arm.com\/processors\/b\/blog\/posts\/armv8-a-architecture-evolution","author":"Brash David","year":"2016","unstructured":"David Brash. Armv8-A architecture evolution. https:\/\/community.arm.com\/processors\/b\/blog\/posts\/armv8-a-architecture-evolution, 2016."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2010.2040971"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2660193.2660224"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.14778\/2735479.2735483"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020989"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151007"},{"key":"e_1_3_2_1_13_1","volume-title":"ISCA","author":"Chhabra Siddhartha","year":"2011","unstructured":"Siddhartha Chhabra and Yan Solihin. i-NVMM: A secure non-volatile main memory system with incremental encryption. In ISCA, 2011."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00051"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522724"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950380"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/563998.564037"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379248"},{"key":"e_1_3_2_1_19_1","volume-title":"SOSP","author":"Condit Jeremy","year":"2009","unstructured":"Jeremy Condit, Edmund B. Nightingale, Christopher Frost, Engin Ipek, Benjamin Lee, Doug Burger, and Derrick Coetzee. Better I\/O through byte-addressable, persistent memory. In SOSP, 2009."},{"key":"e_1_3_2_1_20_1","volume-title":"INFLOW","author":"Das Dhananjoy","year":"2014","unstructured":"Dhananjoy Das, Dulcardo Arteaga, Nisha Talagala, Torben Mathiasen, and Jan Lindstr\u00f6m. NVM compression---hybrid flash-aware application level compression. In INFLOW, 2014."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/1855840.1855856"},{"key":"e_1_3_2_1_22_1","volume-title":"VLDB","author":"DeBrabant Justin","year":"2014","unstructured":"Justin DeBrabant, Joy Arulraj, Andrew Pavlo, Michael Stonebraker, Stanley B. Zdonik, and Subramanya Dulloor. A prolegomenon on OLTP database systems for non-volatile memory. In VLDB, 2014."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1979.11256"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592814"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/HiPC.2016.023"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694353"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.5555\/822080.822806"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3192366.3192367"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00034"},{"key":"e_1_3_2_1_30_1","volume-title":"EuroSys","author":"Ching-Hsiang Hsu Terry","year":"2017","unstructured":"Terry Ching-Hsiang Hsu, Helge Br\u00fcgner, Indrajit Roy, Kimberly Keeton, and Patrick Eugster. NVthreads: Practical persistence for multi-threaded applications. In EuroSys, 2017."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.5555\/3154690.3154757"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.14778\/2735496.2735502"},{"key":"e_1_3_2_1_33_1","volume-title":"Intel architecture instruction set extensions programming reference (319433-034 may","author":"Intel Corporation","year":"2018","unstructured":"Intel Corporation. Intel architecture instruction set extensions programming reference (319433-034 may 2018). https:\/\/software.intel.com\/sites\/default\/files\/managed\/c5\/15\/architecture-instruction-set-extensions-programming-reference.pdf."},{"key":"e_1_3_2_1_34_1","unstructured":"Intel Corporation. An introduction to pmemcheck. http:\/\/pmem.io\/2015\/07\/17\/pmemcheck-basic.html."},{"key":"e_1_3_2_1_35_1","unstructured":"Intel Corporation. Persistent memory programming. https:\/\/pmem.io\/."},{"key":"e_1_3_2_1_36_1","unstructured":"Intel Corporation. Revolutionary memory technology. https:\/\/www.intel.com\/content\/www\/us\/en\/architecture-and-technology\/optane-dc-persistent-memory.html."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872410"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.50"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.69"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080229"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872381"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195709"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/3132747.3132770"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.5555\/2643634.2643678"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.5555\/977395.977673"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_3_2_1_48_1","unstructured":"David Levinthal. Performance Analysis Guide for Intel Core i7 Processor and Intel Xeon 5500 processors. https:\/\/software.intel.com\/sites\/products\/collateral\/hpc\/vtune\/performance_analysis_guide.pdf."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.7873\/DATE2014.102"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.5555\/2930583.2930606"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037714"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00029"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00035"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304015"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-014-9141-x"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/1755913.1755915"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.5555\/2930583.2930607"},{"key":"e_1_3_2_1_58_1","volume-title":"HotStorage","author":"Marathe Virendra J.","year":"2017","unstructured":"Virendra J. Marathe, Margo Seltzer, Steve Byan, and Tim Harris. Persistent Memcached: Bringing legacy code to byte-addressable persistent memory. In HotStorage, 2017."},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.5555\/3026852.3026873"},{"key":"e_1_3_2_1_60_1","unstructured":"David Mulnix. Intel Xeon Processor D product family technical overview. https:\/\/software.intel.com\/en-us\/articles\/intel-xeon-processor-d-product-family-technical-overview."},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.5555\/822080.822823"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037730"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2008.4681832"},{"key":"e_1_3_2_1_64_1","unstructured":"Simo Neuvonen Antoni Wolski Markku Manner and Vilho Raatikka. Telecom application transaction processing benchmark. http:\/\/tatpbenchmark.sourceforge.net\/ 2011."},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.5555\/3277332.3277354"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540724"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665712"},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062205"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830802"},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.5555\/2831143.2831170"},{"key":"e_1_3_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670339"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485971"},{"key":"e_1_3_2_1_76_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.44"},{"key":"e_1_3_2_1_77_1","volume-title":"Workshop on Architectural Support for Security and Anti-Virus","author":"Rogers Brain","year":"2004","unstructured":"Brain Rogers, Yan Solihin, and Milos Prvulovic. Memory predecryption: Hiding the latency overhead of memory encryption. In Workshop on Architectural Support for Security and Anti-Virus, 2004."},{"key":"e_1_3_2_1_78_1","volume-title":"RIPEMD-160, and SHS. INTEGRATION, the VLSI journal, 40(1):3--10","author":"Satoh Akashi","year":"2007","unstructured":"Akashi Satoh and Tadanobu Inoue. ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS. INTEGRATION, the VLSI journal, 40(1):3--10, 2007."},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.5555\/647097.717008"},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815980"},{"key":"e_1_3_2_1_81_1","volume-title":"HPCA","author":"Shafiee Ali","year":"2018","unstructured":"Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari, and Feifei Li. Secure DIMM: Moving ORAM primitives closer to memory. In HPCA, 2018."},{"key":"e_1_3_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835972"},{"key":"e_1_3_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516660"},{"key":"e_1_3_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1145\/782814.782838"},{"key":"e_1_3_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956575"},{"key":"e_1_3_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.22"},{"key":"e_1_3_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.1145\/2892208.2892235"},{"key":"e_1_3_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.2014.2302311"},{"key":"e_1_3_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2018.2863281"},{"key":"e_1_3_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1145\/356989.357005"},{"key":"e_1_3_2_1_92_1","unstructured":"Transaction Processing Performance Council (TPC)). TPC-C. http:\/\/www.tpc.org\/tpcc\/default.asp."},{"key":"e_1_3_2_1_93_1","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592810"},{"key":"e_1_3_2_1_94_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950379"},{"key":"e_1_3_2_1_95_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2774270"},{"key":"e_1_3_2_1_96_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.9"},{"key":"e_1_3_2_1_97_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00043"},{"key":"e_1_3_2_1_98_1","doi-asserted-by":"publisher","DOI":"10.14778\/2732951.2732960"},{"key":"e_1_3_2_1_99_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593220"},{"key":"e_1_3_2_1_100_1","doi-asserted-by":"publisher","DOI":"10.5555\/1025126.1025980"},{"key":"e_1_3_2_1_101_1","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063436"},{"key":"e_1_3_2_1_102_1","doi-asserted-by":"publisher","DOI":"10.5555\/3154690.3154724"},{"key":"e_1_3_2_1_103_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056056"},{"key":"e_1_3_2_1_104_1","doi-asserted-by":"publisher","DOI":"10.5555\/2930583.2930608"},{"key":"e_1_3_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956576"},{"key":"e_1_3_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00040"},{"key":"e_1_3_2_1_107_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694387"},{"key":"e_1_3_2_1_108_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522326"},{"key":"e_1_3_2_1_109_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694370"},{"key":"e_1_3_2_1_110_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540744"},{"key":"e_1_3_2_1_111_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379246"},{"key":"e_1_3_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.5555\/3277332.3277338"},{"key":"e_1_3_2_1_113_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00043"}],"event":{"name":"ISCA '19: The 46th Annual International Symposium on Computer Architecture","location":"Phoenix Arizona","acronym":"ISCA '19","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS\\DATC IEEE Computer Society"]},"container-title":["Proceedings of the 46th International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322206","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3307650.3322206","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:13:37Z","timestamp":1750202017000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322206"}},"subtitle":["optimizing memory and storage support for non-volatile memory systems"],"short-title":[],"issued":{"date-parts":[[2019,6,22]]},"references-count":111,"alternative-id":["10.1145\/3307650.3322206","10.1145\/3307650"],"URL":"https:\/\/doi.org\/10.1145\/3307650.3322206","relation":{},"subject":[],"published":{"date-parts":[[2019,6,22]]},"assertion":[{"value":"2019-06-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}