{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:45:22Z","timestamp":1773193522682,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":123,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,22]],"date-time":"2019-06-22T00:00:00Z","timestamp":1561161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,22]]},"DOI":"10.1145\/3307650.3322231","type":"proceedings-article","created":{"date-parts":[[2019,6,14]],"date-time":"2019-06-14T12:42:33Z","timestamp":1560516153000},"page":"129-142","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":66,"title":["CROW"],"prefix":"10.1145","author":[{"given":"Hasan","family":"Hassan","sequence":"first","affiliation":[{"name":"ETH Z\u00fcrich"}]},{"given":"Minesh","family":"Patel","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}]},{"given":"Jeremie S.","family":"Kim","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich and Carnegie Mellon University"}]},{"given":"A. Giray","family":"Yaglikci","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}]},{"given":"Nandita","family":"Vijaykumar","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich and Carnegie Mellon University"}]},{"given":"Nika Mansouri","family":"Ghiasi","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}]},{"given":"Saugata","family":"Ghose","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich and Carnegie Mellon University"}]}],"member":"320","published-online":{"date-parts":[[2019,6,22]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Arizona State Univ. NIMO Group \"Predictive Technology Model \" http:\/\/ptm.asu.edu\/ 2012."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.164"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/2648668.2648720"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/2616606.2616820"},{"key":"e_1_3_2_1_5_1","unstructured":"K. Chandrasekar et al. \"DRAMPower: Open-Source DRAM Power & Energy Estimation Tool \" http:\/\/www.drampower.info."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901453"},{"key":"e_1_3_2_1_7_1","volume-title":"Improving DRAM Performance by Parallelizing Refreshes with Accesses,\" in HPCA","author":"Chang K. K.","year":"2014","unstructured":"K. K. Chang et al., \"Improving DRAM Performance by Parallelizing Refreshes with Accesses,\" in HPCA, 2014."},{"key":"e_1_3_2_1_8_1","volume-title":"Low-cost Inter-linked Subarrays (LISA): Enabling Fast Inter-subarray Data Movement in DRAM,\" in HPCA","author":"Chang K. K.","year":"2016","unstructured":"K. K. Chang et al., \"Low-cost Inter-linked Subarrays (LISA): Enabling Fast Inter-subarray Data Movement in DRAM,\" in HPCA, 2016."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/3078505.3078590"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750402"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2597652.2597663"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.93"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_3_2_1_15_1","volume-title":"Mediabench II Video: Expediting the Next Generation of Video Systems Research,\" in Electronic Imaging","author":"Fritts J. E.","year":"2005","unstructured":"J. E. Fritts et al., \"Mediabench II Video: Expediting the Next Generation of Video Systems Research,\" in Electronic Imaging, 2005."},{"key":"e_1_3_2_1_16_1","volume-title":"Armor: A Run-Time Memory Hot-Row Detector,\" http:\/\/apt.cs.manchester.ac.uk\/projects\/ARMOR\/RowHammer","author":"Ghasempour M.","year":"2015","unstructured":"M. Ghasempour et al., \"Armor: A Run-Time Memory Hot-Row Detector,\" http:\/\/apt.cs.manchester.ac.uk\/projects\/ARMOR\/RowHammer, 2015."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3309697.3331482"},{"key":"e_1_3_2_1_18_1","volume-title":"Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study,\" arXiv:1902.07609 {cs.AR}","author":"Ghose S.","year":"2019","unstructured":"S. Ghose et al., \"Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study,\" arXiv:1902.07609 {cs.AR}, 2019."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.38"},{"key":"e_1_3_2_1_20_1","volume-title":"Another Flip in the Wall of Rowhammer Defenses,\" in SP","author":"Gruss D.","year":"2018","unstructured":"D. Gruss et al., \"Another Flip in the Wall of Rowhammer Defenses,\" in SP, 2018."},{"key":"e_1_3_2_1_21_1","volume-title":"Rowhammer.js: A Remote Software-Induced Fault Attack in Javascript,\" in DIMVA","author":"Gruss D.","year":"2016","unstructured":"D. Gruss et al., \"Rowhammer.js: A Remote Software-Induced Fault Attack in Javascript,\" in DIMVA, 2016."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2304576.2304613"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2011.6114205"},{"key":"e_1_3_2_1_24_1","volume-title":"On the Retention Time Distribution of Dynamic Random Access Memory (DRAM),\" TED","author":"Hamamoto T.","year":"1998","unstructured":"T. Hamamoto et al., \"On the Retention Time Distribution of Dynamic Random Access Memory (DRAM),\" TED, 1998."},{"key":"e_1_3_2_1_25_1","volume-title":"SimPoint 3.0: Faster and More Flexible Program Phase Analysis,\" JILP","author":"Hamerly G.","year":"2005","unstructured":"G. Hamerly et al., \"SimPoint 3.0: Faster and More Flexible Program Phase Analysis,\" JILP, 2005."},{"key":"e_1_3_2_1_26_1","volume-title":"ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality,\" in HPCA","author":"Hassan H.","year":"2016","unstructured":"H. Hassan et al., \"ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality,\" in HPCA, 2016."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.173"},{"key":"e_1_3_2_1_28_1","volume-title":"A Comparative Analysis of Microarchitecture Effects on CPU and GPU Memory System Behavior,\" in IISWC","author":"Hestness J.","year":"2014","unstructured":"J. Hestness et al., \"A Comparative Analysis of Microarchitecture Effects on CPU and GPU Memory System Behavior,\" in IISWC, 2014."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.52944"},{"key":"e_1_3_2_1_30_1","volume-title":"Moby: A Mobile Benchmark Suite for Architectural Simulators,\" in ISPASS","author":"Huang Y.","year":"2014","unstructured":"Y. Huang et al., \"Moby: A Mobile Benchmark Suite for Architectural Simulators,\" in ISPASS, 2014."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006211"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.21"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669156"},{"key":"e_1_3_2_1_34_1","unstructured":"ITRS Reports http:\/\/www.itrs2.net\/itrs-reports.html."},{"key":"e_1_3_2_1_35_1","volume-title":"DDR3 SDRAM Standard","author":"Solid State Technology Assn EDEC","year":"2012","unstructured":"JEDEC Solid State Technology Assn., \"JESD79-3F: DDR3 SDRAM Standard,\" July 2012."},{"key":"e_1_3_2_1_36_1","volume-title":"Low Power Double Data Rate 4 (LPDDR4) Standard","author":"Solid State Technology Assn EDEC","year":"2017","unstructured":"JEDEC Solid State Technology Assn., \"JESD209-4B: Low Power Double Data Rate 4 (LPDDR4) Standard,\" March 2017."},{"key":"e_1_3_2_1_37_1","volume-title":"DDR4 SDRAM Standard","author":"Solid State Technology Assn EDEC","year":"2017","unstructured":"JEDEC Solid State Technology Assn., \"JESD79-4B: DDR4 SDRAM Standard,\" June 2017."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2818950.2818964"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2745844.2745867"},{"key":"e_1_3_2_1_40_1","volume-title":"Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling,\" in The Memory Forum","author":"Kang U.","year":"2014","unstructured":"U. Kang et al., \"Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling,\" in The Memory Forum, 2014."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2592000"},{"key":"e_1_3_2_1_42_1","volume-title":"PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM,\" in DSN","author":"Khan S.","year":"2016","unstructured":"S. Khan et al., \"PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM,\" in DSN, 2016."},{"key":"e_1_3_2_1_43_1","volume-title":"A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM,\" CAL","author":"Khan S.","year":"2016","unstructured":"S. Khan et al., \"A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM,\" CAL, 2016."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123945"},{"key":"e_1_3_2_1_45_1","volume-title":"Architectural Support for Mitigating Row Hammering in DRAM Memories,\" CAL","author":"Kim D.-H.","year":"2015","unstructured":"D.-H. Kim et al., \"Architectural Support for Mitigating Row Hammering in DRAM Memories,\" CAL, 2015."},{"key":"e_1_3_2_1_46_1","volume-title":"Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines,\" in ICCD","author":"Kim J.","year":"2018","unstructured":"J. Kim et al., \"Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines,\" in ICCD, 2018."},{"key":"e_1_3_2_1_47_1","volume-title":"The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices,\" in HPCA","author":"Kim J. S.","year":"2018","unstructured":"J. S. Kim et al., \"The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices,\" in HPCA, 2018."},{"key":"e_1_3_2_1_48_1","volume-title":"D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput,\" in HPCA","author":"Kim J. S.","year":"2019","unstructured":"J. S. Kim et al., \"D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput,\" in HPCA, 2019."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.5555\/646948.712555"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817524"},{"key":"e_1_3_2_1_51_1","volume-title":"A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs,\" EDL","author":"Kim K.","year":"2009","unstructured":"K. Kim and J. Lee, \"A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs,\" EDL, 2009."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665726"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337202"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"e_1_3_2_1_56_1","volume-title":"Analysis of Coupling Noise Between Adjacent Bit Lines in Megabit DRAMs,\" JSSC","author":"Konishi Y.","year":"1989","unstructured":"Y. Konishi et al., \"Analysis of Coupling Noise Between Adjacent Bit Lines in Megabit DRAMs,\" JSSC, 1989."},{"key":"e_1_3_2_1_57_1","volume-title":"Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case,\" in HPCA","author":"Lee D.","year":"2015","unstructured":"D. Lee et al., \"Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case,\" in HPCA, 2015."},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522354"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/2832911"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/3078505.3078533"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.51"},{"key":"e_1_3_2_1_62_1","volume-title":"TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering,\" CAL","author":"Lee E.","year":"2018","unstructured":"E. Lee et al., \"TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering,\" CAL, 2018."},{"key":"e_1_3_2_1_63_1","volume-title":"Nethammer: Inducing Rowhammer Faults Through Network Requests,\" arXiv","author":"Lipp M.","year":"2018","unstructured":"M. Lipp et al., \"Nethammer: Inducing Rowhammer Faults Through Network Requests,\" arXiv, 2018."},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337161"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485928"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/2248487.1950391"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830827"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2014.50"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.462.0187"},{"key":"e_1_3_2_1_71_1","unstructured":"J. D. McCalpin \"STREAM: Sustainable Memory Bandwidth in High Performance Computers \" https:\/\/www.cs.virginia.edu\/stream\/."},{"key":"e_1_3_2_1_72_1","unstructured":"Micron Technology Inc. \"RLDRAM 2 and 3 Specifications \" http:\/\/www.micron.com\/products\/dram\/rldram-memory."},{"key":"e_1_3_2_1_73_1","unstructured":"Micron Technology Inc. \"x64 Mobile LPDDR4 SDRAM Datasheet \" https:\/\/prod.micron.com\/~\/media\/documents\/products\/data-sheet\/dram\/mobile-dram\/low-power-dram\/lpddr4\/272b_z9am_qdp_mobile_lpddr4.pdf."},{"key":"e_1_3_2_1_74_1","volume-title":"The Origin of Variable Retention Time in DRAM,\" in IEDM","author":"Mori Y.","year":"2005","unstructured":"Y. Mori et al., \"The Origin of Variable Retention Time in DRAM,\" in IEDM, 2005."},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.5555\/1362903.1362921"},{"key":"e_1_3_2_1_76_1","volume-title":"Understanding and Mitigating Refresh Overheads in High-Density DDR4 DRAM Systems,\" in ISCA","author":"Mukundan J.","year":"2013","unstructured":"J. Mukundan et al., \"Understanding and Mitigating Refresh Overheads in High-Density DDR4 DRAM Systems,\" in ISCA, 2013."},{"key":"e_1_3_2_1_78_1","volume-title":"A Systems Architecture Perspective,\" IMW","author":"Mutlu O.","year":"2013","unstructured":"O. Mutlu, \"Memory Scaling: A Systems Architecture Perspective,\" IMW, 2013."},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","unstructured":"O. Mutlu \"The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser \" in DATE 2017.","DOI":"10.5555\/3130379.3130643"},{"key":"e_1_3_2_1_80_1","volume-title":"RowHammer: A Retrospective,\" TCAD","author":"Mutlu O.","year":"2019","unstructured":"O. Mutlu and J. S. Kim, \"RowHammer: A Retrospective,\" TCAD, 2019."},{"key":"e_1_3_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"e_1_3_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.14529\/jsfi140302"},{"key":"e_1_3_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522355"},{"key":"e_1_3_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1145\/2579669"},{"key":"e_1_3_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451137"},{"key":"e_1_3_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1007\/11556930_48"},{"key":"e_1_3_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080242"},{"key":"e_1_3_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"e_1_3_2_1_89_1","unstructured":"Rambus Inc. \"DRAM Power Model \" http:\/\/www.rambus.com\/energy\/. 2016."},{"key":"e_1_3_2_1_90_1","volume-title":"Flip Feng Shui: Hammering a Needle in the Software Stack,\" in USENIX Sec","author":"Razavi K.","year":"2016","unstructured":"K. Razavi et al., \"Flip Feng Shui: Hammering a Needle in the Software Stack,\" in USENIX Sec., 2016."},{"key":"e_1_3_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.5555\/582628.825134"},{"key":"e_1_3_2_1_92_1","volume-title":"DRAM Variable Retention Time,\" in IEDM","author":"Restle P. J.","year":"1992","unstructured":"P. J. Restle et al., \"DRAM Variable Retention Time,\" in IEDM, 1992."},{"key":"e_1_3_2_1_93_1","volume-title":"Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory,\" TVLSI","author":"Riho Y.","year":"2014","unstructured":"Y. Riho and K. Nakazato, \"Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory,\" TVLSI, 2014."},{"key":"e_1_3_2_1_94_1","doi-asserted-by":"publisher","unstructured":"S. Rixner \"Memory Controller Optimizations for Web Servers \" in MICRO 2004. 10.1109\/MICRO.2004.22","DOI":"10.1109\/MICRO.2004.22"},{"key":"e_1_3_2_1_95_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"e_1_3_2_1_96_1","unstructured":"SAFARI Research Group \"CROW --- GitHub Repository \" https:\/\/github.com\/CMU-SAFARI\/CROW."},{"key":"e_1_3_2_1_97_1","unstructured":"SAFARI Research Group \"Ramulator: A DRAM Simulator --- GitHub Repository \" https:\/\/github.com\/CMU-SAFARI\/ramulator."},{"key":"e_1_3_2_1_98_1","volume-title":"Fast Cycle RAM (FCRAM)","author":"Sato Y.","year":"1998","unstructured":"Y. Sato et al., \"Fast Cycle RAM (FCRAM); A 20-ns Random Row Access, Pipe-Lined Operating DRAM,\" in VLSIC, 1998."},{"key":"e_1_3_2_1_99_1","volume-title":"Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges,\" https:\/\/googleprojectzero.blogspot.com\/2015\/03\/exploiting-dram-rowhammer-bug-to-gain.html","author":"Seaborn M.","year":"2015","unstructured":"M. Seaborn and T. Dullien, \"Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges,\" https:\/\/googleprojectzero.blogspot.com\/2015\/03\/exploiting-dram-rowhammer-bug-to-gain.html, 2015."},{"key":"e_1_3_2_1_100_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"e_1_3_2_1_101_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"e_1_3_2_1_102_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830820"},{"key":"e_1_3_2_1_103_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00057"},{"key":"e_1_3_2_1_104_1","volume-title":"Symbiotic Jobscheduling for a Simultaneous Mutlithreading Processor,\" ASPLOS","author":"Snavely A.","year":"2000","unstructured":"A. Snavely and D. M. Tullsen, \"Symbiotic Jobscheduling for a Simultaneous Mutlithreading Processor,\" ASPLOS, 2000."},{"key":"e_1_3_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485955"},{"key":"e_1_3_2_1_106_1","unstructured":"Standard Performance Evaluation Corp. \"SPEC CPU<sup>\u00ae<\/sup> 2006 \" http:\/\/www.spec.org\/cpu2006\/ 2006."},{"key":"e_1_3_2_1_107_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.22"},{"key":"e_1_3_2_1_108_1","volume-title":"The Blacklisting Memory Scheduler: Achieving High Performance and Fairness at Low Cost,\" in ICCD","author":"Subramanian L.","year":"2014","unstructured":"L. Subramanian et al., \"The Blacklisting Memory Scheduler: Achieving High Performance and Fairness at Low Cost,\" in ICCD, 2014."},{"key":"e_1_3_2_1_109_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2526003"},{"key":"e_1_3_2_1_110_1","volume-title":"Defeating Software Mitigations Against Rowhammer: A Surgical Precision Hammer,\" in RAID","author":"Tatar A.","year":"2018","unstructured":"A. Tatar et al., \"Defeating Software Mitigations Against Rowhammer: A Surgical Precision Hammer,\" in RAID, 2018."},{"key":"e_1_3_2_1_111_1","unstructured":"Transaction Processing Performance Council \"TPC Benchmarks \" http:\/\/www.tpc.org\/."},{"key":"e_1_3_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"key":"e_1_3_2_1_113_1","doi-asserted-by":"publisher","DOI":"10.1145\/2976749.2978406"},{"key":"e_1_3_2_1_114_1","volume-title":"Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM,\" in HPCA","author":"Venkatesan R.","year":"2006","unstructured":"R. Venkatesan et al., \"Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM,\" in HPCA, 2006."},{"key":"e_1_3_2_1_115_1","doi-asserted-by":"publisher","unstructured":"T. Vogelsang \"Understanding the Energy Consumption of Dynamic Random Access Memories \" in MICRO 2010. 10.1109\/MICRO.2010.42","DOI":"10.1109\/MICRO.2010.42"},{"key":"e_1_3_2_1_116_1","volume-title":"Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration,\" in MICRO","author":"Wang Y.","year":"2018","unstructured":"Y. Wang et al., \"Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration,\" in MICRO, 2018."},{"key":"e_1_3_2_1_117_1","doi-asserted-by":"publisher","DOI":"10.5555\/3241094.3241097"},{"key":"e_1_3_2_1_118_1","volume-title":"A Meta-Stable Leakage Phenomenon in DRAM Charge Storage - Variable Hold Time,\" in IEDM","author":"Yaney D.","year":"1987","unstructured":"D. Yaney et al., \"A Meta-Stable Leakage Phenomenon in DRAM Charge Storage - Variable Hold Time,\" in IEDM, 1987."},{"key":"e_1_3_2_1_119_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665724"},{"key":"e_1_3_2_1_120_1","doi-asserted-by":"publisher","DOI":"10.5555\/2755753.2755862"},{"key":"e_1_3_2_1_121_1","volume-title":"Restore Truncation for Performance Improvement in Future DRAM Systems,\" in HPCA","author":"Zhang X.","year":"2016","unstructured":"X. Zhang et al.,\"Restore Truncation for Performance Improvement in Future DRAM Systems,\" in HPCA, 2016."},{"key":"e_1_3_2_1_122_1","volume-title":"New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration,\" TED","author":"Zhao W.","year":"2006","unstructured":"W. Zhao and Y. Cao, \"New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration,\" TED, 2006."},{"key":"e_1_3_2_1_123_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830792"},{"key":"e_1_3_2_1_124_1","volume-title":"Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests and Commands to Be Issued Out of Order,\" U.S. Patent No. 5,630,096","author":"Zuravleff W. K.","year":"1997","unstructured":"W. K. Zuravleff and T. Robinson, \"Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests and Commands to Be Issued Out of Order,\" U.S. Patent No. 5,630,096, 1997."}],"event":{"name":"ISCA '19: The 46th Annual International Symposium on Computer Architecture","location":"Phoenix Arizona","acronym":"ISCA '19","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS\\DATC IEEE Computer Society"]},"container-title":["Proceedings of the 46th International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322231","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3307650.3322231","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:54:05Z","timestamp":1750204445000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322231"}},"subtitle":["a low-cost substrate for improving DRAM performance, energy efficiency, and reliability"],"short-title":[],"issued":{"date-parts":[[2019,6,22]]},"references-count":123,"alternative-id":["10.1145\/3307650.3322231","10.1145\/3307650"],"URL":"https:\/\/doi.org\/10.1145\/3307650.3322231","relation":{},"subject":[],"published":{"date-parts":[[2019,6,22]]},"assertion":[{"value":"2019-06-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}