{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:49:03Z","timestamp":1773193743396,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":75,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,22]],"date-time":"2019-06-22T00:00:00Z","timestamp":1561161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1730158 and 1527034"],"award-info":[{"award-number":["1730158 and 1527034"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["JUMP CRISP"],"award-info":[{"award-number":["JUMP CRISP"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,22]]},"DOI":"10.1145\/3307650.3322237","type":"proceedings-article","created":{"date-parts":[[2019,6,14]],"date-time":"2019-06-14T12:42:33Z","timestamp":1560516153000},"page":"802-815","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":159,"title":["FloatPIM"],"prefix":"10.1145","author":[{"given":"Mohsen","family":"Imani","sequence":"first","affiliation":[{"name":"UC San Diego"}]},{"given":"Saransh","family":"Gupta","sequence":"additional","affiliation":[{"name":"UC San Diego"}]},{"given":"Yeseong","family":"Kim","sequence":"additional","affiliation":[{"name":"UC San Diego"}]},{"given":"Tajana","family":"Rosing","sequence":"additional","affiliation":[{"name":"UC San Diego"}]}],"member":"320","published-online":{"date-parts":[[2019,6,22]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"2017 IEEE International Symposium on, IEEE","author":"Song L.","year":"2017","unstructured":"L. Song, X. Qian, H. Li, and Y. Chen, \"Pipelayer: A pipelined reram-based accelerator for deep learning,\" in High Performance Computer Architecture (HPCA), 2017 IEEE International Symposium on, IEEE, 2017."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.12"},{"key":"e_1_3_2_1_3_1","volume-title":"Deep learning,\" nature","author":"LeCun Y.","unstructured":"Y. LeCun, Y. Bengio, and G. Hinton, \"Deep learning,\" nature, vol. 521, no. 7553, p. 436, 2015."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.neunet.2014.09.003"},{"key":"e_1_3_2_1_5_1","first-page":"184","volume-title":"Learning a deep convolutional network for image super-resolution,\" in European conference on computer vision","author":"Dong C.","year":"2014","unstructured":"C. Dong, C. C. Loy, K. He, and X. Tang, \"Learning a deep convolutional network for image super-resolution,\" in European conference on computer vision, pp. 184--199, Springer, 2014."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1561\/2000000039"},{"key":"e_1_3_2_1_7_1","volume-title":"J. Schrittwieser, I. Antonoglou, V. Panneershelvam, M. Lanctot, et al., \"Mastering the game of go with deep neural networks and tree search,\" nature","author":"Silver D.","unstructured":"D. Silver, A. Huang, C. J. Maddison, A. Guez, L. Sifre, G. Van Den Driessche, J. Schrittwieser, I. Antonoglou, V. Panneershelvam, M. Lanctot, et al., \"Mastering the game of go with deep neural networks and tree search,\" nature, vol. 529, no. 7587, p. 484, 2016."},{"key":"e_1_3_2_1_8_1","volume-title":"Very deep convolutional networks for large-scale image recognition,\" arXiv preprint arXiv:1409.1556","author":"Simonyan K.","year":"2014","unstructured":"K. Simonyan and A. Zisserman, \"Very deep convolutional networks for large-scale image recognition,\" arXiv preprint arXiv:1409.1556, 2014."},{"key":"e_1_3_2_1_9_1","first-page":"525","volume-title":"Xnor-net: Imagenet classification using binary convolutional neural networks,\" in European Conference on Computer Vision","author":"Rastegari M.","year":"2016","unstructured":"M. Rastegari, V. Ordonez, J. Redmon, and A. Farhadi, \"Xnor-net: Imagenet classification using binary convolutional neural networks,\" in European Conference on Computer Vision, pp. 525--542, Springer, 2016."},{"key":"e_1_3_2_1_10_1","first-page":"1","volume-title":"2016 IEEE International Symposium on","author":"Bojnordi M. N.","year":"2016","unstructured":"M. N. Bojnordi and E. Ipek, \"Memristive boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning,\" in High Performance Computer Architecture (HPCA), 2016 IEEE International Symposium on, pp. 1--13, IEEE, 2016."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.13"},{"key":"e_1_3_2_1_12_1","volume-title":"Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding,\" arXiv preprint arXiv:1510.00149","author":"Han S.","year":"2015","unstructured":"S. Han, H. Mao, and W. J. Dally, \"Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding,\" arXiv preprint arXiv:1510.00149, 2015."},{"key":"e_1_3_2_1_13_1","unstructured":"M. Courbariaux Y. Bengio and J.-P. David \"Training deep neural networks with low precision multiplications \" arXiv preprint arXiv:1412.7024 2014."},{"key":"e_1_3_2_1_14_1","volume-title":"Relaxed quantization for discretized neural networks,\" arXiv preprint arXiv:1810.01875","author":"Louizos C.","year":"2018","unstructured":"C. Louizos, M. Reisser, T. Blankevoort, E. Gavves, and M. Welling, \"Relaxed quantization for discretized neural networks,\" arXiv preprint arXiv:1810.01875, 2018."},{"key":"e_1_3_2_1_15_1","unstructured":"\"Bfloat16 floating point format..\" https:\/\/en.wikipedia.org\/wiki\/Bfloat16_floating-point_format."},{"key":"e_1_3_2_1_16_1","unstructured":"\"Intel xeon processors and intel fpgas..\" https:\/\/venturebeat.com\/2018\/05\/23\/intel-unveils-nervana-neural-net-l-1000-for-accelerated-ai-training\/."},{"key":"e_1_3_2_1_17_1","unstructured":"\"Intel xeon and fpga lines.\" https:\/\/www.top500.org\/news\/intel-lays-out-new-roadmap-for-ai-portfolio\/."},{"key":"e_1_3_2_1_18_1","unstructured":"\"Nnp-l1000.\" https:\/\/www.tomshardware.com\/news\/intel-neural-network-processor-lake-crest 37105.html."},{"key":"e_1_3_2_1_19_1","unstructured":"\"Google cloud..\" https:\/\/cloud.google.com\/tpu\/docs\/tensorflow-ops."},{"key":"e_1_3_2_1_20_1","unstructured":"\"Tpu repository with tensorflow 1.7.0..\" https:\/\/blog.riseml.com\/comparing-google-tpuv2-against-nvidia-v100-on-resnet-50-c2bbb6a51e5e?gi=51a90720b9dd."},{"key":"e_1_3_2_1_21_1","volume-title":"Tensorflow distributions,\" arXiv preprint arXiv:1711.10604","author":"Dillon J. V.","year":"2017","unstructured":"J. V. Dillon, I. Langmore, D. Tran, E. Brevdo, S. Vasudevan, D. Moore, B. Patton, A. Alemi, M. Hoffman, and R. A. Saurous, \"Tensorflow distributions,\" arXiv preprint arXiv:1711.10604, 2017."},{"key":"e_1_3_2_1_22_1","unstructured":"\"Google. 2018-05-08. retrieved 2018-05-23. in many models this is a drop-in replacement for float-32..\" https:\/\/www.youtube.com\/watch?v=vm67WcLzfvc&t=2555."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00039"},{"key":"e_1_3_2_1_24_1","unstructured":"\"Intel and micron produce breakthrough memory technology.. \" http:\/\/newsroom.intel.com\/community\/intel_newsroom\/blog\/2015\/07\/28\/intel-and-micron-produce-breakthrough-memory-technology."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062326"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/3201607.3201632"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196071"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/2999134.2999257"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/34.58871"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240811"},{"key":"e_1_3_2_1_32_1","volume-title":"A complementary resistive switch-based crossbar array adder,\" IEEE journal on emerging and selected topics in circuits and systems","author":"Siemon A.","unstructured":"A. Siemon, S. Menzel, R. Waser, and E. Linn, \"A complementary resistive switch-based crossbar array adder,\" IEEE journal on emerging and selected topics in circuits and systems, vol. 5, no. 1, pp. 64--74, 2015."},{"issue":"10","key":"e_1_3_2_1_33_1","first-page":"2054","article-title":"Memristor-based material implication (IMPLY) logic: design principles and methodologies","volume":"22","author":"Kvatinsky S.","year":"2014","unstructured":"S. Kvatinsky, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, \"Memristor-based material implication (IMPLY) logic: design principles and methodologies,\" TVLSI, vol. 22, no. 10, pp. 2054--2066, 2014.","journal-title":"TVLSI"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1038\/nature08940"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"crossref","unstructured":"B. C. Jang Y. Nam B. J. Koo J. Choi S. G. Im S.-H. K. Park and S.-Y. Choi \"Memristive logic-in-memory integrated circuits for energy-efficient flexible electronics \" Advanced Functional Materials vol. 28 no. 2 2018.","DOI":"10.1002\/adfm.201704725"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2433536"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2570248"},{"key":"e_1_3_2_1_38_1","volume-title":"ACM","author":"Imani M.","year":"2017","unstructured":"M. Imani, S. Gupta, and T. Rosing, \"Ultra-efficient processing in-memory for data intensive applications,\" in Proceedings of the 54th Annual Design Automation Conference 2017, p. 6, ACM, 2017."},{"key":"e_1_3_2_1_39_1","volume-title":"Haj-Ali et al., \"Efficient algorithms for in-memory fixed point multiplication using magic,\" in IEEE ISCAS","author":"A.","year":"2018","unstructured":"A. Haj-Ali et al., \"Efficient algorithms for in-memory fixed point multiplication using magic,\" in IEEE ISCAS, IEEE, 2018."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.5555\/3130379.3130624"},{"key":"e_1_3_2_1_41_1","first-page":"476","volume-title":"Overcoming the challenges of crossbar resistive memory architectures,\" in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","author":"Xu C.","year":"2015","unstructured":"C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, and Y. Xie, \"Overcoming the challenges of crossbar resistive memory architectures,\" in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pp. 476--488, IEEE, 2015."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.053631140"},{"key":"e_1_3_2_1_43_1","first-page":"770","article-title":"Deep residual learning for image recognition","author":"He K.","year":"2016","unstructured":"K. He, X. Zhang, S. Ren, and J. Sun, \"Deep residual learning for image recognition,\" in Proceedings of the IEEE conference on computer vision and pattern recognition, pp. 770--778, 2016.","journal-title":"Proceedings of the IEEE conference on computer vision and pattern recognition"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2538618"},{"key":"e_1_3_2_1_45_1","unstructured":"F. Chollet \"keras.\" https:\/\/github.com\/fchollet\/keras 2015."},{"key":"e_1_3_2_1_46_1","volume-title":"Tensorflow: Large-scale machine learning on heterogeneous distributed systems,\" arXiv preprint arXiv:1603.04467","author":"Abadi M.","year":"2016","unstructured":"M. Abadi, A. Agarwal, P. Barham, E. Brevdo, Z. Chen, C. Citro, G. S. Corrado, A. Davis, J. Dean, M. Devin, et al., \"Tensorflow: Large-scale machine learning on heterogeneous distributed systems,\" arXiv preprint arXiv:1603.04467, 2016."},{"key":"e_1_3_2_1_47_1","first-page":"15","volume-title":"Nvsim: A circuit-level performance, energy, and area model for emerging non-volatile memory,\" in Emerging Memory Technologies","author":"Dong X.","year":"2014","unstructured":"X. Dong, C. Xu, N. Jouppi, and Y. Xie, \"Nvsim: A circuit-level performance, energy, and area model for emerging non-volatile memory,\" in Emerging Memory Technologies, pp. 15--50, Springer, 2014."},{"key":"e_1_3_2_1_48_1","volume-title":"Synopsys,\" Inc., see http:\/\/www.synopsys.com","author":"Compiler D.","year":"2000","unstructured":"D. Compiler, R. User, and M. Guide, \"Synopsys,\" Inc., see http:\/\/www.synopsys.com, 2000."},{"key":"e_1_3_2_1_49_1","first-page":"1","article-title":"Going deeper with convolutions","author":"Szegedy C.","year":"2015","unstructured":"C. Szegedy, W. Liu, Y. Jia, P. Sermanet, S. Reed, D. Anguelov, D. Erhan, V. Vanhoucke, and A. Rabinovich, \"Going deeper with convolutions,\" in Proceedings of the IEEE conference on computer vision and pattern recognition, pp. 1--9, 2015.","journal-title":"Proceedings of the IEEE conference on computer vision and pattern recognition"},{"key":"e_1_3_2_1_50_1","volume-title":"Squeezenet: Alexnet-level accuracy with 50x fewer parameters and &lt","author":"Iandola F. N.","year":"2016","unstructured":"F. N. Iandola, S. Han, M. W. Moskewicz, K. Ashraf, W. J. Dally, and K. Keutzer, \"Squeezenet: Alexnet-level accuracy with 50x fewer parameters and &lt; 0.5 mb model size,\" arXiv preprint arXiv:1602.07360, 2016."},{"key":"e_1_3_2_1_51_1","volume-title":"Mixed precision training,\" arXiv preprint arXiv:1710.03740","author":"Micikevicius P.","year":"2017","unstructured":"P. Micikevicius, S. Narang, J. Alben, G. Diamos, E. Elsen, D. Garcia, B. Ginsburg, M. Houston, O. Kuchaev, G. Venkatesh, et al., \"Mixed precision training,\" arXiv preprint arXiv:1710.03740, 2017."},{"key":"e_1_3_2_1_52_1","volume-title":"End-to-end dnn training with block floating point arithmetic,\" arXiv preprint arXiv:1804.01526","author":"Drumond M.","year":"2018","unstructured":"M. Drumond, T. Lin, M. Jaggi, and B. Falsafi, \"End-to-end dnn training with block floating point arithmetic,\" arXiv preprint arXiv:1804.01526, 2018."},{"key":"e_1_3_2_1_53_1","volume-title":"Mixed precision training of convolutional neural networks using integer operations,\" arXiv preprint arXiv:1802.00930","author":"Das D.","year":"2018","unstructured":"D. Das, N. Mellempudi, D. Mudigere, D. Kalamkar, S. Avancha, K. Banerjee, S. Sridharan, K. Vaidyanathan, B. Kaul, E. Georganas, et al., \"Mixed precision training of convolutional neural networks using integer operations,\" arXiv preprint arXiv:1802.00930, 2018."},{"key":"e_1_3_2_1_54_1","volume-title":"High-accuracy low-precision training,\" arXiv preprint arXiv:1803.03383","author":"De Sa C.","year":"2018","unstructured":"C. De Sa, M. Leszczynski, J. Zhang, A. Marzoev, C. R. Aberger, K. Olukotun, and C. R\u00e9, \"High-accuracy low-precision training,\" arXiv preprint arXiv:1803.03383, 2018."},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195659"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123982"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/2644865.2541967"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00061"},{"key":"e_1_3_2_1_59_1","volume-title":"Ucnn: Exploiting computational reuse in deep neural networks via weight repetition,\" arXiv preprint arXiv:1804.06508","author":"Hegde K.","year":"2018","unstructured":"K. Hegde, J. Yu, R. Agrawal, M. Yan, M. Pellauer, and C. W. Fletcher, \"Ucnn: Exploiting computational reuse in deep neural networks via weight repetition,\" arXiv preprint arXiv:1804.06508, 2018."},{"key":"e_1_3_2_1_60_1","volume-title":"ACM","author":"Ding C.","year":"2017","unstructured":"C. Ding, S. Liao, Y. Wang, Z. Li, N. Liu, Y. Zhuo, C. Wang, X. Qian, Y. Bai, G. Yuan, et al., \"C ir cnn: accelerating and compressing deep neural networks using block-circulant weight matrices,\" in Proceedings of the 50th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 395--408, ACM, 2017."},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","unstructured":"E. Nurvitadhi G. Venkatesh J. Sim D. Marr R. Huang J. Ong Gee Hock Y. T. Liew K. Srivatsan D. Moss S. Subhaschandra et al. \"Can fpgas beat gpus in accelerating next-generation deep neural networks? \" in Proceedings of the 2017 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays pp. 5--14 ACM 2017. 10.1145\/3020078.3021740","DOI":"10.1145\/3020078.3021740"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.30"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"e_1_3_2_1_64_1","volume-title":"Neural cache: Bit-serial in-cache acceleration of deep neural networks,\" arXiv preprint arXiv:1805.03718","author":"Eckert C.","year":"2018","unstructured":"C. Eckert, X. Wang, J. Wang, A. Subramaniyan, R. Iyer, D. Sylvester, D. Blaauw, and R. Das, \"Neural cache: Bit-serial in-cache acceleration of deep neural networks,\" arXiv preprint arXiv:1805.03718, 2018."},{"key":"e_1_3_2_1_65_1","volume-title":"ACM","author":"Li S.","year":"2017","unstructured":"S. Li, D. Niu, K. T. Malladi, H. Zheng, B. Brennan, and Y. Xie, \"Drisa: A dram-based reconfigurable in-situ accelerator,\" in Proceedings of the 50th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 288--301, ACM, 2017."},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.53"},{"key":"e_1_3_2_1_67_1","volume-title":"Rapidnn: In-memory deep neural network acceleration framework,\" arXiv preprint arXiv:1806.05794","author":"Imani M.","year":"2018","unstructured":"M. Imani, M. Samragh, Y. Kim, S. Gupta, F. Koushanfar, and T. Rosing, \"Rapidnn: In-memory deep neural network acceleration framework,\" arXiv preprint arXiv:1806.05794, 2018."},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2903055"},{"key":"e_1_3_2_1_69_1","first-page":"1155","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE)","author":"Imani M.","year":"2018","unstructured":"M. Imani, S. Gupta, and T. Rosing, \"Genpim: Generalized processing in-memory to accelerate data intensive applications,\" in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1155--1158, IEEE, 2018."},{"key":"e_1_3_2_1_70_1","first-page":"1","volume-title":"Rnsnet: In-memory neural network acceleration using residue number system,\" in 2018 IEEE International Conference on Rebooting Computing (ICRC)","author":"Salamat S.","year":"2018","unstructured":"S. Salamat, M. Imani, S. Gupta, and T. Rosing, \"Rnsnet: In-memory neural network acceleration using residue number system,\" in 2018 IEEE International Conference on Rebooting Computing (ICRC), pp. 1--12, IEEE, 2018."},{"key":"e_1_3_2_1_71_1","first-page":"445","volume-title":"Exploring hyperdimensional associative memory,\" in 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)","author":"Imani M.","year":"2017","unstructured":"M. Imani, A. Rahimi, D. Kong, T. Rosing, and J. M. Rabaey, \"Exploring hyperdimensional associative memory,\" in 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 445--456, IEEE, 2017."},{"key":"e_1_3_2_1_72_1","first-page":"25","volume-title":"Orchard: Visual object recognition accelerator based on approximate in-memory processing,\" in 2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Kim Y.","year":"2017","unstructured":"Y. Kim, M. Imani, and T. Rosing, \"Orchard: Visual object recognition accelerator based on approximate in-memory processing,\" in 2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 25--32, IEEE, 2017."},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1145\/3218603.3218631"},{"key":"e_1_3_2_1_74_1","volume-title":"ACM","author":"Zhou M.","year":"2019","unstructured":"M. Zhou, M. Imani, S. Gupta, Y. Kim, and T. Rosing, \"Gram: graph processing in a reram-based computational memory,\" in Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp. 591--596, ACM, 2019."},{"key":"e_1_3_2_1_75_1","article-title":"Nvquery: Efficient query processing in non-volatile memory","author":"Imani M.","year":"2018","unstructured":"M. Imani, S. Gupta, S. Sharma, and T. Rosing, \"Nvquery: Efficient query processing in non-volatile memory,\" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"}],"event":{"name":"ISCA '19: The 46th Annual International Symposium on Computer Architecture","location":"Phoenix Arizona","acronym":"ISCA '19","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS\\DATC IEEE Computer Society"]},"container-title":["Proceedings of the 46th International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322237","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3307650.3322237","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3307650.3322237","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:54:06Z","timestamp":1750204446000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322237"}},"subtitle":["in-memory acceleration of deep neural network training with high precision"],"short-title":[],"issued":{"date-parts":[[2019,6,22]]},"references-count":75,"alternative-id":["10.1145\/3307650.3322237","10.1145\/3307650"],"URL":"https:\/\/doi.org\/10.1145\/3307650.3322237","relation":{},"subject":[],"published":{"date-parts":[[2019,6,22]]},"assertion":[{"value":"2019-06-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}