{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,6]],"date-time":"2026-06-06T20:16:17Z","timestamp":1780776977812,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":59,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,22]],"date-time":"2019-06-22T00:00:00Z","timestamp":1561161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Air Force Research Laboratory and Defense Advanced Research Projects Agency","award":["FA8650-18-2-7865"],"award-info":[{"award-number":["FA8650-18-2-7865"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,22]]},"DOI":"10.1145\/3307650.3322249","type":"proceedings-article","created":{"date-parts":[[2019,6,14]],"date-time":"2019-06-14T12:42:33Z","timestamp":1560516153000},"page":"615-628","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":27,"title":["Scalable interconnects for reconfigurable spatial architectures"],"prefix":"10.1145","author":[{"given":"Yaqi","family":"Zhang","sequence":"first","affiliation":[{"name":"Stanford University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alexander","family":"Rucker","sequence":"additional","affiliation":[{"name":"Stanford University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Matthew","family":"Vilim","sequence":"additional","affiliation":[{"name":"Stanford University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Raghu","family":"Prabhakar","sequence":"additional","affiliation":[{"name":"Stanford University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"William","family":"Hwang","sequence":"additional","affiliation":[{"name":"Stanford University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kunle","family":"Olukotun","sequence":"additional","affiliation":[{"name":"Stanford University"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,6,22]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1999946.1999966"},{"key":"e_1_3_2_1_2_1","unstructured":"Amazon AWS. {n. d.}. Amazon EC2 F1 Instances. https:\/\/aws.amazon.com\/ec2\/instance-types\/f1."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/968878.969078"},{"key":"e_1_3_2_1_5_1","unstructured":"Ivo Bolsens. 2006. Programming Modern FPGAs International Forum on Embedded Multiprocessor SoC Keynote. http:\/\/www.xilinx.com\/univ\/mpsoc2006keynote.pdf."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1764631.1764633"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2037211"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.4.31"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/2821589"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01386390"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/1898953.1899045"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00012"},{"key":"e_1_3_2_1_14_1","volume-title":"HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). 126--137","author":"Gao Mingyu","year":"2016","unstructured":"Mingyu Gao and Christos Kozyrakis. 2016. HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). 126--137."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","unstructured":"Eric Garcia and Maya Gupta. 2009. Lattice Regression. In Advances in Neural Information Processing Systems. 594--602.","DOI":"10.5555\/2984093.2984160"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/139669.140384"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300982"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749755"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/1320302.1320836"},{"key":"e_1_3_2_1_20_1","volume-title":"2016 IEEE Hot Chips 28 Symposium (HCS). 1--27","author":"Guo Kaiyuan","year":"2016","unstructured":"Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Song Yao, Song Han, Yu Wang, and Huazhong Yang. 2016. From Model to FPGA: Software-Hardware Co-design for Efficient Neural Network Acceleration. In 2016 IEEE Hot Chips 28 Symposium (HCS). 1--27."},{"key":"e_1_3_2_1_21_1","volume-title":"Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip. VLSI design 2007","author":"Hansson Andreas","year":"2007","unstructured":"Andreas Hansson, Kees Goossens, and Andrei R\u0103dulescu. 2007. Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip. VLSI design 2007 (2007)."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/368434.368597"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435296"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.2200\/S00772ED1V01Y201704CAC040"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1155\/2011\/745147"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062262"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2025280"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555782"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3192366.3192379"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.20"},{"key":"e_1_3_2_1_32_1","unstructured":"Rainer Kress. 1996. A Fast Reconfigurable ALU for Xputers."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1561\/1000000005"},{"key":"e_1_3_2_1_34_1","volume-title":"Hugo De Man, and Rudy Lauwereins","author":"Mei Bingfeng","year":"2003","unstructured":"Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, and Rudy Lauwereins. 2003. ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In Field Programmable Logic and Application, Peter Y. K. Cheung and George A. Constantinides (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg, 61--70."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168878"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.5555\/795657.795822"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996809"},{"key":"e_1_3_2_1_38_1","unstructured":"Chris Nicol. {n. d.}. A Coarse Grain Reconfigurable Array (CGRA) for Statically Scheduled Data Flow Computing. https:\/\/wavecomp.ai\/wp-content\/uploads\/2018\/12\/WP_CGRA.pdf"},{"key":"e_1_3_2_1_39_1","series-title":"Hot Chips 30","volume-title":"Xilinx Project Everest: 'HW\/SW Programmable Engine'","author":"Noguera Juanjo","unstructured":"Juanjo Noguera, Chris Dick, Vinod Kathail, Gaurav Singh, Kees Vissers, and Ralph Wittig. 2018. Xilinx Project Everest: 'HW\/SW Programmable Engine' (Hot Chips 30). http:\/\/www.hotchips.org\/hc30\/2conf\/2.03_Xilinx_Juanjo_XilinxSWPEHotChips20180819.pdf"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080255"},{"key":"e_1_3_2_1_41_1","series-title":"Hot Chips 26","volume-title":"SDA: Software-Defined Accelerator for LargeScale DNN Systems","author":"Ouyang Jian","year":"2014","unstructured":"Jian Ouyang, Shiding Lin, Wei Qi, Yong Wang, Bo Yu, and Song Jiang. 2014. SDA: Software-Defined Accelerator for LargeScale DNN Systems (Hot Chips 26)."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1755951.1755902"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485935"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","unstructured":"Hyunchul Park Yongjun Park and Scott Mahlke. 2009. Polymorphic Pipeline Array: A Flexible Multicore Accelerator with Virtualized Execution for Mobile Multimedia Applications. In 2009 42nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 370--380. 10.1145\/1669112.1669160","DOI":"10.1145\/1669112.1669160"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059881"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080256"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1957.tb01515.x"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665678"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736065.1736069"},{"key":"e_1_3_2_1_50_1","volume-title":"30th Annual International Symposium on Computer Architecture, 2003. Proceedings. 422--433","author":"Sankaralingam Karthikeyan","unstructured":"Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, and Charles R. Moore. 2003. Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture. In 30th Annual International Symposium on Computer Architecture, 2003. Proceedings. 422--433."},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071443"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233307.1233308"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.5555\/822080.822819"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2386883"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272293"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105748"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2013.05.002"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.5555\/1320302.1320834"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876095"}],"event":{"name":"ISCA '19: The 46th Annual International Symposium on Computer Architecture","location":"Phoenix Arizona","acronym":"ISCA '19","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS\\DATC IEEE Computer Society"]},"container-title":["Proceedings of the 46th International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322249","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3307650.3322249","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:54:06Z","timestamp":1750204446000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322249"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6,22]]},"references-count":59,"alternative-id":["10.1145\/3307650.3322249","10.1145\/3307650"],"URL":"https:\/\/doi.org\/10.1145\/3307650.3322249","relation":{},"subject":[],"published":{"date-parts":[[2019,6,22]]},"assertion":[{"value":"2019-06-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}