{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,14]],"date-time":"2026-03-14T17:58:10Z","timestamp":1773511090530,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,22]],"date-time":"2019-06-22T00:00:00Z","timestamp":1561161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,22]]},"DOI":"10.1145\/3307650.3322252","type":"proceedings-article","created":{"date-parts":[[2019,6,14]],"date-time":"2019-06-14T12:42:33Z","timestamp":1560516153000},"page":"157-168","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":51,"title":["Anubis"],"prefix":"10.1145","author":[{"given":"Kazi Abu","family":"Zubair","sequence":"first","affiliation":[{"name":"University of Central Florida"}]},{"given":"Amro","family":"Awad","sequence":"additional","affiliation":[{"name":"University of Central Florida"}]}],"member":"320","published-online":{"date-parts":[[2019,6,22]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.24"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522320"},{"key":"e_1_3_2_1_3_1","volume-title":"et al., \"A 130.7mm2 2-layer 32gb reram memory device in 24nm technology,\" in IEEE International Solid-State Circuits Conference Digest of Technical Papers","author":"L.","year":"2013","unstructured":"T.-Y.L. et al., \"A 130.7mm2 2-layer 32gb reram memory device in 24nm technology,\" in IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"e_1_3_2_1_5_1","article-title":"Advances and future prospects of spin-transfer torque random access memory","author":"E. C.","year":"2010","unstructured":"E. C. et al., \"Advances and future prospects of spin-transfer torque random access memory,\" in IEEE Transactions on Magnetics, Jun. 2010.","journal-title":"IEEE Transactions on Magnetics"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.22"},{"key":"e_1_3_2_1_7_1","volume-title":"Osiris: A low-cost mechanism to enable restoration of secure non-volatile memories,\" in 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO","author":"Ye M.","year":"2018","unstructured":"M. Ye, C. Hughes, and A. Awad, \"Osiris: A low-cost mechanism to enable restoration of secure non-volatile memories,\" in 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 2018), 2018."},{"key":"e_1_3_2_1_8_1","volume-title":"Crash consistency in encrypted non-volatile main memory systems,\" in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)","author":"Liu J. R. S.","year":"2018","unstructured":"J. R. S. Liu, A. Kolli and S. Khan, \"Crash consistency in encrypted non-volatile main memory systems,\" in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.44"},{"key":"e_1_3_2_1_10_1","unstructured":"\"Enhancing High-Performance Computing with Persistent Memory Technology.\" https:\/\/software.intel.com\/en-us\/articles\/enhancing-high-performance-computing-with-persistent-memory-technology. Accessed: 2018-12-07."},{"key":"e_1_3_2_1_11_1","unstructured":"\"Amazon.com Goes Down Loses $66 240 Per Minute.\" https:\/\/www.forbes.com\/sites\/kellyclay\/2013\/08\/19\/amazon-com-goes-down-loses-66240-per-minute\/#68dc6b6b495c. Accessed: 2019-02-19."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2980024.2872377"},{"key":"e_1_3_2_1_13_1","unstructured":"A. Ruddof \"Deprecating the pcommit instruction \" 2016."},{"key":"e_1_3_2_1_14_1","volume-title":"Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode","author":"Edirisooriya S. J.","year":"2017","unstructured":"S. J. Edirisooriya, S. R. Nagesh, B. R. Monson, and P. Kumar, \"Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode,\" Feb. 9 2017. US Patent App. 14\/816,445."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_17_1","volume-title":"Report 2016\/204","author":"Gueron S.","year":"2016","unstructured":"S. Gueron, \"A memory encryption engine suitable for general purpose processors.\" Cryptology ePrint Archive, Report 2016\/204, 2016. https:\/\/eprint.iacr.org\/2016\/204."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","unstructured":"M. Taassori A. Shafiee and R. Balasubramonian \"Vault: Reducing paging overheads in sgx with efficient integrity verification structures \" in Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems pp. 665--678 2018. 10.1145\/3173162.3177155","DOI":"10.1145\/3173162.3177155"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00041"},{"key":"e_1_3_2_1_20_1","first-page":"454","volume-title":"Synergy: Rethinking secure-memory design for error-correcting memories,\" in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)","author":"Saileshwar G.","year":"2018","unstructured":"G. Saileshwar, P. J. Nair, P. Ramrakhyani, W. Elsasser, and M. K. Qureshi, \"Synergy: Rethinking secure-memory design for error-correcting memories,\" in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 454--465, IEEE, 2018."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3102980.3102982"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555758"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_24_1","volume-title":"Persistency for integrity-protected and encrypted non-volatile memories,\" in Proceedings of the 46th International Symposium on Computer Architecture (ISCA)","author":"Awad A.","year":"2019","unstructured":"A. Awad, M. Ye, Y. Solihin, L. Njilla, and K. Abu Zubair, \"Triad-nvm: Persistency for integrity-protected and encrypted non-volatile memories,\" in Proceedings of the 46th International Symposium on Computer Architecture (ISCA), 2019."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1961295.1950380"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540744"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080229"},{"key":"e_1_3_2_1_28_1","volume-title":"MA)","author":"Zuo P.","year":"2018","unstructured":"P. Zuo and Y. Hua, \"Secpm: a secure and persistent memory system for nonvolatile memory,\" in 10th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage 18), (Boston, MA), USENIX Association, 2018."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830802"}],"event":{"name":"ISCA '19: The 46th Annual International Symposium on Computer Architecture","location":"Phoenix Arizona","acronym":"ISCA '19","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS\\DATC IEEE Computer Society"]},"container-title":["Proceedings of the 46th International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322252","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3307650.3322252","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:54:06Z","timestamp":1750204446000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322252"}},"subtitle":["ultra-low overhead and recovery time for secure non-volatile memories"],"short-title":[],"issued":{"date-parts":[[2019,6,22]]},"references-count":29,"alternative-id":["10.1145\/3307650.3322252","10.1145\/3307650"],"URL":"https:\/\/doi.org\/10.1145\/3307650.3322252","relation":{},"subject":[],"published":{"date-parts":[[2019,6,22]]},"assertion":[{"value":"2019-06-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}