{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:46:27Z","timestamp":1772725587156,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":132,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,22]],"date-time":"2019-06-22T00:00:00Z","timestamp":1561161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"SRC","award":["2719.001"],"award-info":[{"award-number":["2719.001"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,22]]},"DOI":"10.1145\/3307650.3322266","type":"proceedings-article","created":{"date-parts":[[2019,6,14]],"date-time":"2019-06-14T12:42:33Z","timestamp":1560516153000},"page":"629-642","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":71,"title":["CoNDA"],"prefix":"10.1145","author":[{"given":"Amirali","family":"Boroumand","sequence":"first","affiliation":[{"name":"Carnegie Mellon University"}]},{"given":"Saugata","family":"Ghose","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}]},{"given":"Minesh","family":"Patel","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}]},{"given":"Hasan","family":"Hassan","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}]},{"given":"Brandon","family":"Lucia","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}]},{"given":"Rachata","family":"Ausavarungnirun","sequence":"additional","affiliation":[{"name":"KMUTNB and Carnegie Mellon University"}]},{"given":"Kevin","family":"Hsieh","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}]},{"given":"Nastaran","family":"Hajinazar","sequence":"additional","affiliation":[{"name":"Simon Fraser University and Carnegie Mellon University"}]},{"given":"Krishna T.","family":"Malladi","sequence":"additional","affiliation":[{"name":"Samsung Semiconductor, Inc."}]},{"given":"Hongzhong","family":"Zheng","sequence":"additional","affiliation":[{"name":"Samsung Semiconductor, Inc."}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich and Carnegie Mellon University"}]}],"member":"320","published-online":{"date-parts":[[2019,6,22]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.4"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126908.3126918"},{"key":"e_1_3_2_1_3_1","volume-title":"A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,\" in ISCA","author":"Ahn J.","year":"2015","unstructured":"J. Ahn et al., \"A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,\" in ISCA, 2015."},{"key":"e_1_3_2_1_4_1","volume-title":"Locality-Aware Processing-in-Memory Architecture,\" in ISCA","author":"Ahn J.","year":"2015","unstructured":"J. Ahn et al., \"PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture,\" in ISCA, 2015."},{"key":"e_1_3_2_1_5_1","volume-title":"Data Reorganization in Memory using 3D-Stacked DRAM,\" in ISCA","author":"Akin B.","year":"2015","unstructured":"B. Akin et al., \"Data Reorganization in Memory using 3D-Stacked DRAM,\" in ISCA, 2015."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195669"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"e_1_3_2_1_8_1","volume-title":"The Case for Heterogeneous HTAP,\" in CIDR","author":"Appuswamy R.","year":"2017","unstructured":"R. Appuswamy et al., \"The Case for Heterogeneous HTAP,\" in CIDR, 2017."},{"key":"e_1_3_2_1_9_1","volume-title":"Bridging the Archipelago Between Row-Stores and Column-Stores for Hybrid Workloads,\" in SIGMOD","author":"Arulraj J.","year":"2016","unstructured":"J. Arulraj et al., \"Bridging the Archipelago Between Row-Stores and Column-Stores for Hybrid Workloads,\" in SIGMOD, 2016."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/362686.362692"},{"key":"e_1_3_2_1_12_1","volume-title":"LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory,\" IEEE CAL","author":"Boroumand A.","year":"2017","unstructured":"A. Boroumand et al., \"LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory,\" IEEE CAL, 2017."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173177"},{"key":"e_1_3_2_1_14_1","volume-title":"LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures,\" arXiv:1706.03162 {cs.AR}","author":"Boroumand A.","year":"2017","unstructured":"A. Boroumand et al., \"LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures,\" arXiv:1706.03162 {cs.AR}, 2017."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/297805.297827"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250697"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.13"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508255"},{"key":"e_1_3_2_1_19_1","unstructured":"DRAMSim2 http:\/\/www.eng.umd.edu\/blj\/dramsim\/."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514197"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080233"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.9"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123983"},{"key":"e_1_3_2_1_25_1","volume-title":"Farmahini-Farahani et al., \"NDA: Near-DRAM Acceleration Architecture Leveraging Commodity DRAM Devices and Standard Memory Modules,\" in HPCA","author":"A.","year":"2015","unstructured":"A. Farmahini-Farahani et al., \"NDA: Near-DRAM Acceleration Architecture Leveraging Commodity DRAM Devices and Standard Memory Modules,\" in HPCA, 2015."},{"key":"e_1_3_2_1_26_1","volume-title":"Practical Near-Data Processing for In-Memory Analytics Frameworks,\" in PACT","author":"Gao M.","year":"2015","unstructured":"M. Gao et al., \"Practical Near-Data Processing for In-Memory Analytics Frameworks,\" in PACT, 2015."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037702"},{"key":"e_1_3_2_1_28_1","volume-title":"The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption,\" in Beyond-CMOS Technologies for Next Generation Computer Design","author":"Ghose S.","year":"2019","unstructured":"S. Ghose et al., \"The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption,\" in Beyond-CMOS Technologies for Next Generation Computer Design, 2019."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3309697.3331482"},{"key":"e_1_3_2_1_30_1","volume-title":"Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study,\" arXiv:1902.07609 {cs.AR}","author":"Ghose S.","year":"2019","unstructured":"S. Ghose et al., \"Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study,\" arXiv:1902.07609 {cs.AR}, 2019."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195692"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","unstructured":"J. R. Goodman \"Using Cache Memory to Reduce Processor-Memory Traffic \" in ISCA 1983. 10.1145\/800046.801647","DOI":"10.1145\/800046.801647"},{"key":"e_1_3_2_1_33_1","unstructured":"Google LLC \"TensorFlow: Mobile \" https:\/\/www.tensorflow.org\/mobile\/."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080234"},{"key":"e_1_3_2_1_35_1","volume-title":"3D-Stacked Memory-Side Acceleration: Accelerator and System Design,\" in WoNDP","author":"Guo Q.","year":"2014","unstructured":"Q. Guo et al., \"3D-Stacked Memory-Side Acceleration: Accelerator and System Design,\" in WoNDP, 2014."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3155287"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195707"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830800"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291020"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006711"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195712"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.46"},{"key":"e_1_3_2_1_43_1","volume-title":"Cache-Coherent Distributed Shared Memory: Perspectives on Its Development and Future Challenges,\" Proc","author":"Hennessy J.","year":"1999","unstructured":"J. Hennessy et al., \"Cache-Coherent Distributed Shared Memory: Perspectives on Its Development and Future Challenges,\" Proc. IEEE, 1999."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_3_2_1_46_1","volume-title":"Accelerating Linked-List Traversal Through Near-Data Processing,\" in PACT","author":"Hong B.","year":"2016","unstructured":"B. Hong et al., \"Accelerating Linked-List Traversal Through Near-Data Processing,\" in PACT, 2016."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001159"},{"key":"e_1_3_2_1_48_1","volume-title":"Mechanisms, Evaluation,\" in ICCD","author":"Hsieh K.","year":"2016","unstructured":"K. Hsieh et al., \"Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation,\" in ICCD, 2016."},{"key":"e_1_3_2_1_49_1","unstructured":"Hybrid Memory Cube Consortium \"Hybrid Memory Cube Specification 2.1 \" 2015."},{"key":"e_1_3_2_1_50_1","unstructured":"Intel Corp. \"Intel Chipset 89xx Series \" http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/solution-briefs\/scaling-acceleration-capacity-brief.pdf."},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/2588555.2612174"},{"key":"e_1_3_2_1_52_1","volume-title":"Hybrid Memory Cube New DRAM Architecture Increases Density and Performance,\" in VLSIT","author":"Jeddeloh J.","year":"2012","unstructured":"J. Jeddeloh and B. Keeth, \"Hybrid Memory Cube New DRAM Architecture Increases Density and Performance,\" in VLSIT, 2012."},{"key":"e_1_3_2_1_53_1","volume-title":"High Bandwidth Memory (HBM) DRAM","author":"Solid State Technology Assn EDEC","year":"2013","unstructured":"JEDEC Solid State Technology Assn., \"JESD235: High Bandwidth Memory (HBM) DRAM,\" October 2013."},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037736"},{"key":"e_1_3_2_1_55_1","volume-title":"FlexRAM: Toward an Advanced Intelligent Memory System,\" in ICCD","author":"Kang Y.","year":"2012","unstructured":"Y. Kang et al., \"FlexRAM: Toward an Advanced Intelligent Memory System,\" in ICCD, 2012."},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.89"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854291"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE.2011.5767867"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.41"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126908.3126965"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.5555\/2523721.2523744"},{"key":"e_1_3_2_1_62_1","volume-title":"ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers,\" in HPCA","author":"Kim Y.","year":"2010","unstructured":"Y. Kim et al., \"ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers,\" in HPCA, 2010."},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"e_1_3_2_1_65_1","volume-title":"Janus: Transaction Processing of Navigation and Analytic Graph Queries on Many-Core Servers,\" in CIDR","author":"Kimura H.","year":"2017","unstructured":"H. Kimura et al., \"Janus: Transaction Processing of Navigation and Analytic Graph Queries on Many-Core Servers,\" in CIDR, 2017."},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.14778\/2856318.2856321"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540748"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1994.108"},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1145\/277830.277852"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750421"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/319566.319567"},{"key":"e_1_3_2_1_72_1","volume-title":"Oracle Database In-Memory: A Dual Format In-Memory Database,\" in ICDE","author":"Lahiri T.","year":"2015","unstructured":"T. Lahiri et al., \"Oracle Database In-Memory: A Dual Format In-Memory Database,\" in ICDE, 2015."},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1145\/2832911"},{"key":"e_1_3_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876435"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485926"},{"key":"e_1_3_2_1_76_1","volume-title":"Processing-in-Memory for Energy-Efficient Neural Network Training: A Heterogeneous Approach,\" in MICRO","author":"Liu J.","year":"2018","unstructured":"J. Liu et al., \"Processing-in-Memory for Energy-Efficient Neural Network Training: A Heterogeneous Approach,\" in MICRO, 2018."},{"key":"e_1_3_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.49"},{"key":"e_1_3_2_1_78_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123941"},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339673"},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1145\/3035918.3035959"},{"key":"e_1_3_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605400"},{"key":"e_1_3_2_1_82_1","unstructured":"MemSQL Inc. \"MemSQL \" http:\/\/www.memsql.com\/."},{"key":"e_1_3_2_1_83_1","volume-title":"Sort vs. Hash Join Revisited for Near-Memory Execution,\" in ASBD","author":"Mirzadeh N.","year":"2007","unstructured":"N. Mirzadeh et al., \"Sort vs. Hash Join Revisited for Near-Memory Execution,\" in ASBD, 2007."},{"key":"e_1_3_2_1_84_1","volume-title":"LogTM: Log-Based Transactional Memory,\" in HPCA","author":"Moore K. E.","year":"2006","unstructured":"K. E. Moore et al., \"LogTM: Log-Based Transactional Memory,\" in HPCA, 2006."},{"key":"e_1_3_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"e_1_3_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"e_1_3_2_1_87_1","volume-title":"Processing Data Where It Makes Sense: Enabling In-Memory Computation,\" MICPRO","author":"Mutlu O.","year":"2019","unstructured":"O. Mutlu et al., \"Processing Data Where It Makes Sense: Enabling In-Memory Computation,\" MICPRO, 2019."},{"key":"e_1_3_2_1_88_1","volume-title":"GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks,\" in HPCA","author":"Nai L.","year":"2017","unstructured":"L. Nai et al., \"GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks,\" in HPCA, 2017."},{"key":"e_1_3_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037715"},{"key":"e_1_3_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694350"},{"key":"e_1_3_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279387"},{"key":"e_1_3_2_1_92_1","doi-asserted-by":"publisher","DOI":"10.1145\/800015.808204"},{"key":"e_1_3_2_1_93_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"e_1_3_2_1_94_1","volume-title":"Scheduling Techniques for GPU Architectures with Processing-in-Memory Capabilities,\" in PACT","author":"Pattnaik A.","year":"2016","unstructured":"A. Pattnaik et al., \"Scheduling Techniques for GPU Architectures with Processing-in-Memory Capabilities,\" in PACT, 2016."},{"key":"e_1_3_2_1_95_1","volume-title":"Near-Memory Address Translation,\" in PACT","author":"Picorel J.","year":"2017","unstructured":"J. Picorel et al., \"Near-Memory Address Translation,\" in PACT, 2017."},{"key":"e_1_3_2_1_96_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540747"},{"key":"e_1_3_2_1_97_1","volume-title":"NDC: Analyzing the Impact of 3D-Stacked Memory+Logic Devices on MapReduce Workloads,\" in ISPASS","author":"Pugsley S. H.","year":"2014","unstructured":"S. H. Pugsley et al., \"NDC: Analyzing the Impact of 3D-Stacked Memory+Logic Devices on MapReduce Workloads,\" in ISPASS, 2014."},{"key":"e_1_3_2_1_98_1","doi-asserted-by":"publisher","DOI":"10.5555\/563998.564036"},{"key":"e_1_3_2_1_99_1","volume-title":"MachSuite: Benchmarks for Accelerator Design and Customized Architectures,\" in IISWC","author":"Reagen B.","year":"2014","unstructured":"B. Reagen et al., \"MachSuite: Benchmarks for Accelerator Design and Customized Architectures,\" in IISWC, 2014."},{"key":"e_1_3_2_1_100_1","doi-asserted-by":"publisher","DOI":"10.5555\/1331699.1331713"},{"key":"e_1_3_2_1_101_1","unstructured":"SAP SE \"SAP HANA \" http:\/\/www.hana.sap.com\/."},{"key":"e_1_3_2_1_102_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665697"},{"key":"e_1_3_2_1_103_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2434872"},{"key":"e_1_3_2_1_104_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"e_1_3_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"e_1_3_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2015.374"},{"key":"e_1_3_2_1_107_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195697"},{"key":"e_1_3_2_1_108_1","volume-title":"Towards Cache-Friendly Hardware Accelerators,\" in SCAW","author":"Shao Y. S.","year":"2015","unstructured":"Y. S. Shao et al., \"Towards Cache-Friendly Hardware Accelerators,\" in SCAW, 2015."},{"key":"e_1_3_2_1_109_1","author":"Shavit N.","year":"1997","unstructured":"N. Shavit and D. Touitou, \"Software Transactional Memory,\" Distributed Computing, 1997.","journal-title":"\"Software Transactional Memory,\" Distributed Computing"},{"key":"e_1_3_2_1_110_1","volume-title":"Bull.","author":"Shaw D. E.","year":"1981","unstructured":"D. E. Shaw et al., \"The NON-VON Database Machine: A Brief Overview,\" IEEE Database Eng. Bull., 1981."},{"key":"e_1_3_2_1_111_1","doi-asserted-by":"publisher","DOI":"10.1145\/2442516.2442530"},{"key":"e_1_3_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830821"},{"key":"e_1_3_2_1_113_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317867"},{"key":"e_1_3_2_1_114_1","unstructured":"Stanford Network Analysis Project http:\/\/snap.stanford.edu\/."},{"key":"e_1_3_2_1_115_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339650"},{"key":"e_1_3_2_1_116_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1970.5008902"},{"key":"e_1_3_2_1_117_1","volume-title":"Bull.","author":"Stonebraker M.","year":"2013","unstructured":"M. Stonebraker and A. Weisberg, \"The VoltDB Main Memory DBMS.\" IEEE Data Eng. Bull., 2013."},{"key":"e_1_3_2_1_118_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2014.2380198"},{"key":"e_1_3_2_1_119_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123954"},{"key":"e_1_3_2_1_120_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE.2013.6544839"},{"key":"e_1_3_2_1_121_1","volume-title":"Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies,\" in MICRO","author":"Tsai P.","year":"2018","unstructured":"P. Tsai et al., \"Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies,\" in MICRO, 2018."},{"key":"e_1_3_2_1_122_1","volume-title":"ICPS 2005","author":"Vallejo E.","year":"2005","unstructured":"E. Vallejo et al., \"Implementing Kilo-Instruction Multiprocessors,\" in ICPS 2005, 2005."},{"key":"e_1_3_2_1_123_1","volume-title":"Observations and Opportunities in Architecting Shared Virtual Memory for Heterogeneous Systems,\" in ISPASS","author":"Vesely J.","year":"2016","unstructured":"J. Vesely et al., \"Observations and Opportunities in Architecting Shared Virtual Memory for Heterogeneous Systems,\" in ISPASS, 2016."},{"key":"e_1_3_2_1_124_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250696"},{"key":"e_1_3_2_1_125_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541961"},{"key":"e_1_3_2_1_126_1","doi-asserted-by":"publisher","DOI":"10.1145\/2771937.2771945"},{"key":"e_1_3_2_1_127_1","volume-title":"Processing-in-Memory Enabled Graphics Processors for 3D Rendering,\" in HPCA","author":"Xie C.","year":"2017","unstructured":"C. Xie et al., \"Processing-in-Memory Enabled Graphics Processors for 3D Rendering,\" in HPCA, 2017."},{"key":"e_1_3_2_1_128_1","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600222"},{"key":"e_1_3_2_1_129_1","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600213"},{"key":"e_1_3_2_1_130_1","volume-title":"GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition,\" in HPCA","author":"Zhang M.","year":"2018","unstructured":"M. Zhang et al., \"GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition,\" in HPCA, 2018."},{"key":"e_1_3_2_1_131_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665749"},{"key":"e_1_3_2_1_132_1","doi-asserted-by":"publisher","DOI":"10.5555\/774861.774871"}],"event":{"name":"ISCA '19: The 46th Annual International Symposium on Computer Architecture","location":"Phoenix Arizona","acronym":"ISCA '19","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS\\DATC IEEE Computer Society"]},"container-title":["Proceedings of the 46th International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322266","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3307650.3322266","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:54:06Z","timestamp":1750204446000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3307650.3322266"}},"subtitle":["efficient cache coherence support for near-data accelerators"],"short-title":[],"issued":{"date-parts":[[2019,6,22]]},"references-count":132,"alternative-id":["10.1145\/3307650.3322266","10.1145\/3307650"],"URL":"https:\/\/doi.org\/10.1145\/3307650.3322266","relation":{},"subject":[],"published":{"date-parts":[[2019,6,22]]},"assertion":[{"value":"2019-06-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}