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Code Optim."],"published-print":{"date-parts":[[2019,6,30]]},"abstract":"<jats:p>\n            Inexpensive DRAMs have created new opportunities for in-memory data analytics. However, the major bottleneck in such systems is high memory access latency. Traditionally, this problem is solved with large cache hierarchies that only benefit\n            <jats:italic>regular<\/jats:italic>\n            applications. Alternatively, many data-intensive applications exhibit\n            <jats:italic>irregular<\/jats:italic>\n            behavior. Hardware multithreading can better cope with high latency seen in such applications. This article implements a multithreaded prototype (MTP) on FPGAs for the relational selection operator that exhibits control flow irregularity. On a standard TPC-H query evaluation, MTP achieves a bandwidth utilization of 83%, while the CPU and the GPU implementations achieve 61% and 64%, respectively. Besides being bandwidth efficient, MTP is also 14.2\u00d7 and 4.2\u00d7 more power efficient than CPU and GPU, respectively.\n          <\/jats:p>","DOI":"10.1145\/3310229","type":"journal-article","created":{"date-parts":[[2019,4,10]],"date-time":"2019-04-10T19:55:16Z","timestamp":1554926116000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads"],"prefix":"10.1145","volume":"16","author":[{"given":"Prerna","family":"Budhkar","sequence":"first","affiliation":[{"name":"University of California, Riverside, USA"}]},{"given":"Ildar","family":"Absalyamov","sequence":"additional","affiliation":[{"name":"University of California, Riverside, USA"}]},{"given":"Vasileios","family":"Zois","sequence":"additional","affiliation":[{"name":"University of California, Riverside, USA"}]},{"given":"Skyler","family":"Windh","sequence":"additional","affiliation":[{"name":"University of California, Riverside, USA"}]},{"given":"Walid A.","family":"Najjar","sequence":"additional","affiliation":[{"name":"University of California, Riverside, USA"}]},{"given":"Vassilis J.","family":"Tsotras","sequence":"additional","affiliation":[{"name":"University of California, Riverside, USA"}]}],"member":"320","published-online":{"date-parts":[[2019,4,9]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"NETEZZA. 2014. http:\/\/www.ibm.com\/software\/data\/netezza\/.  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