{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:35:00Z","timestamp":1750221300055,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,4,30]],"date-time":"2019-04-30T00:00:00Z","timestamp":1556582400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,4,30]]},"DOI":"10.1145\/3310273.3323069","type":"proceedings-article","created":{"date-parts":[[2019,5,8]],"date-time":"2019-05-08T14:11:36Z","timestamp":1557324696000},"page":"251-255","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Designing a secure DRAM+NVM hybrid memory module"],"prefix":"10.1145","author":[{"given":"Wang","family":"Xu","sequence":"first","affiliation":[{"name":"University of Massachusetts Amherst, Amherst, Massachusetts"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Israel","family":"Koren","sequence":"additional","affiliation":[{"name":"University of Massachusetts Amherst, Amherst, Massachusetts"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,4,30]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2546199"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155673"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.30"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.19"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485957"},{"key":"e_1_3_2_1_7_1","volume-title":"DDR4 DIMM Devices with Hybrid DRAM & NVM for Big Data Performances at Low Cost, https:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2016\/20160810_S202A_Lee.pdf","author":"Lee X.","year":"2016","unstructured":"X. Lee , F. Longnos , S. Chen and W. Yang , \" DDR4 DIMM Devices with Hybrid DRAM & NVM for Big Data Performances at Low Cost, https:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2016\/20160810_S202A_Lee.pdf \", 2016 X. Lee, F. Longnos, S. Chen and W. Yang, \"DDR4 DIMM Devices with Hybrid DRAM & NVM for Big Data Performances at Low Cost, https:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2016\/20160810_S202A_Lee.pdf\", 2016"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-018-0034-5"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1002\/sec.1071"},{"key":"e_1_3_2_1_10_1","first-page":"333","volume-title":"IEEE\/IFIP International Conference on Dependable Systems and Networks","author":"Kong J.","year":"2010","unstructured":"J. Kong and H. Zhou , \" Improving Privacy and Lifetime of PCM-Based Main Memory \", IEEE\/IFIP International Conference on Dependable Systems and Networks , pp. 333 -- 342 , 2010 J. Kong and H. Zhou, \"Improving Privacy and Lifetime of PCM-Based Main Memory\", IEEE\/IFIP International Conference on Dependable Systems and Networks, pp. 333--342, 2010"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000086"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522314"},{"key":"e_1_3_2_1_13_1","volume-title":"https:\/\/eprint.iacr.org\/2016\/204.pdf","author":"Gueron S.","year":"2016","unstructured":"S. Gueron , \" A Memroy Encryption Engine Suitable for General Purpose Processors\" , https:\/\/eprint.iacr.org\/2016\/204.pdf , 2016 S. Gueron, \"A Memroy Encryption Engine Suitable for General Purpose Processors\", https:\/\/eprint.iacr.org\/2016\/204.pdf, 2016"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-016-1104-y"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2629677"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3085572"},{"key":"e_1_3_2_1_17_1","unstructured":"Micron DDR4 SDRAM https:\/\/www.micron.com  Micron DDR4 SDRAM https:\/\/www.micron.com"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_19_1","first-page":"19","article-title":"Memory Bandwidth and Machine Balance in Current High Performance Computers","volume":"2","author":"McCalpin J. D.","year":"1995","unstructured":"J. D. McCalpin , \" Memory Bandwidth and Machine Balance in Current High Performance Computers \", IEEE Computer Architecture Newsletter , vol 2 , pp. 19 -- 25 , 1995 J. D. McCalpin, \"Memory Bandwidth and Machine Balance in Current High Performance Computers\", IEEE Computer Architecture Newsletter, vol 2, pp.19--25, 1995","journal-title":"IEEE Computer Architecture Newsletter"},{"volume-title":"Persistent Memory Performance, https:\/\/www.micron.com\/~\/media\/documents\/products\/product-flyer\/nvdimm_flyer.pdf","year":"2016","key":"e_1_3_2_1_20_1","unstructured":"Micron's Nonvolatile DIMMs : Persistent Memory Performance, https:\/\/www.micron.com\/~\/media\/documents\/products\/product-flyer\/nvdimm_flyer.pdf , 2016 Micron's Nonvolatile DIMMs: Persistent Memory Performance, https:\/\/www.micron.com\/~\/media\/documents\/products\/product-flyer\/nvdimm_flyer.pdf, 2016"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/3130379.3130595"},{"key":"e_1_3_2_1_22_1","volume-title":"Reliable Secure Efficient Physical Unclonable Functions, https:\/\/pdfs.semanticscholar.org\/9967\/fc5062e649a8fdc76e5bf2137208bd47f6da.pdf","author":"Bhargava M.","year":"2013","unstructured":"M. Bhargava , Reliable Secure Efficient Physical Unclonable Functions, https:\/\/pdfs.semanticscholar.org\/9967\/fc5062e649a8fdc76e5bf2137208bd47f6da.pdf , 2013 M. Bhargava, Reliable Secure Efficient Physical Unclonable Functions, https:\/\/pdfs.semanticscholar.org\/9967\/fc5062e649a8fdc76e5bf2137208bd47f6da.pdf, 2013"},{"key":"e_1_3_2_1_23_1","volume-title":"The IBM z14 Microprocessor Chip Set and Architectural Enhancements, ftp:\/\/public.dhe.ibm.com\/s390\/zos\/racf\/pdf\/ny_naspa_2017_10_z14_overview.pdf","author":"Bradbury J.","year":"2017","unstructured":"J. Bradbury , The IBM z14 Microprocessor Chip Set and Architectural Enhancements, ftp:\/\/public.dhe.ibm.com\/s390\/zos\/racf\/pdf\/ny_naspa_2017_10_z14_overview.pdf , 2017 J. Bradbury, The IBM z14 Microprocessor Chip Set and Architectural Enhancements, ftp:\/\/public.dhe.ibm.com\/s390\/zos\/racf\/pdf\/ny_naspa_2017_10_z14_overview.pdf, 2017"}],"event":{"name":"CF '19: Computing Frontiers Conference","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Alghero Italy","acronym":"CF '19"},"container-title":["Proceedings of the 16th ACM International Conference on Computing Frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3310273.3323069","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3310273.3323069","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:13:17Z","timestamp":1750212797000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3310273.3323069"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4,30]]},"references-count":23,"alternative-id":["10.1145\/3310273.3323069","10.1145\/3310273"],"URL":"https:\/\/doi.org\/10.1145\/3310273.3323069","relation":{},"subject":[],"published":{"date-parts":[[2019,4,30]]},"assertion":[{"value":"2019-04-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}