{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,7]],"date-time":"2026-04-07T21:56:51Z","timestamp":1775599011351,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,2]],"date-time":"2019-06-02T00:00:00Z","timestamp":1559433600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Grantov\u00e1 Agentura \u00f0esk\u00e9 Republiky","award":["19-10137S"],"award-info":[{"award-number":["19-10137S"]}]},{"name":"Ministerstvo \u00f0kolstv\u00ed, Ml\u00e1de\u00f0e a T\u00f0lov\u00f0chovy","award":["CZ.02.2.69\/0.0\/0.0\/ 16_027\/0008371"],"award-info":[{"award-number":["CZ.02.2.69\/0.0\/0.0\/ 16_027\/0008371"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,2]]},"DOI":"10.1145\/3316781.3317781","type":"proceedings-article","created":{"date-parts":[[2019,5,23]],"date-time":"2019-05-23T18:07:13Z","timestamp":1558634833000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":65,"title":["autoAx"],"prefix":"10.1145","author":[{"given":"Vojtech","family":"Mrazek","sequence":"first","affiliation":[{"name":"IT4Innovations Centre of Excellence, Brno University of Technology, Czech Republic and Institute of Computer Engineering, Vienna University of Technology (TU Wien), Austria"}]},{"given":"Muhammad Abdullah","family":"Hanif","sequence":"additional","affiliation":[{"name":"Institute of Computer Engineering, Vienna University of Technology (TU Wien), Austria"}]},{"given":"Zdenek","family":"Vasicek","sequence":"additional","affiliation":[{"name":"IT4Innovations Centre of Excellence, Brno University of Technology, Czech Republic"}]},{"given":"Lukas","family":"Sekanina","sequence":"additional","affiliation":[{"name":"IT4Innovations Centre of Excellence, Brno University of Technology, Czech Republic"}]},{"given":"Muhammad","family":"Shafique","sequence":"additional","affiliation":[{"name":"Institute of Computer Engineering, Vienna University of Technology (TU Wien), Austria"}]}],"member":"320","published-online":{"date-parts":[[2019,6,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00029"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2873289"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062306"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/3094124"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744863"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2027626"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2605382"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2605382"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/3130379.3130438"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967005"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062314"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744778"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2014.2336175"},{"key":"e_1_3_2_1_14_1","volume-title":"Automation Test in Europe Conf. 1367--1372","author":"Venkataramani S."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228504"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","unstructured":"G. Zervakis S. Xydis etal 2018. Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints. IEEE Trans. Circuits Syst. II Exp. Briefs (2018).  G. Zervakis S. Xydis et al. 2018. Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints. IEEE Trans. Circuits Syst. II Exp. Briefs (2018).","DOI":"10.1109\/TCSII.2018.2869025"}],"event":{"name":"DAC '19: The 56th Annual Design Automation Conference 2019","location":"Las Vegas NV USA","acronym":"DAC '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 56th Annual Design Automation Conference 2019"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3317781","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3316781.3317781","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:08:03Z","timestamp":1750208883000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3317781"}},"subtitle":["An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components"],"short-title":[],"issued":{"date-parts":[[2019,6,2]]},"references-count":16,"alternative-id":["10.1145\/3316781.3317781","10.1145\/3316781"],"URL":"https:\/\/doi.org\/10.1145\/3316781.3317781","relation":{},"subject":[],"published":{"date-parts":[[2019,6,2]]},"assertion":[{"value":"2019-06-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}