{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:35:09Z","timestamp":1773246909130,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,2]],"date-time":"2019-06-02T00:00:00Z","timestamp":1559433600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,2]]},"DOI":"10.1145\/3316781.3317857","type":"proceedings-article","created":{"date-parts":[[2019,5,23]],"date-time":"2019-05-23T18:07:13Z","timestamp":1558634833000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":77,"title":["Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism"],"prefix":"10.1145","author":[{"given":"Erick Carvajal","family":"Barboza","sequence":"first","affiliation":[{"name":"Texas A&M University"}]},{"given":"Nishchal","family":"Shukla","sequence":"additional","affiliation":[{"name":"Texas A&M University"}]},{"given":"Yiran","family":"Chen","sequence":"additional","affiliation":[{"name":"Duke University"}]},{"given":"Jiang","family":"Hu","sequence":"additional","affiliation":[{"name":"Texas A&M University"}]}],"member":"320","published-online":{"date-parts":[[2019,6,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382667"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1010933404324"},{"key":"e_1_3_2_1_3_1","volume-title":"Asia and South Pacific Design Automation Conference (ASP-DAC). 178--185","author":"Chan W. J.","unstructured":"W. J. Chan , K. Y. Chung , A. B. Kahng , N. D. MacDonald , and S. Nath . 2016. Learning-based prediction of embedded memory timing failures during initial floorplan design . In Asia and South Pacific Design Automation Conference (ASP-DAC). 178--185 . W. J. Chan, K. Y. Chung, A. B. Kahng, N. D. MacDonald, and S. Nath. 2016. Learning-based prediction of embedded memory timing failures during initial floorplan design. In Asia and South Pacific Design Automation Conference (ASP-DAC). 178--185."},{"key":"e_1_3_2_1_4_1","volume-title":"International Conference On Computer Aided Design (ICCAD). 621--625","author":"Chang H.","unstructured":"H. Chang and S. S. Sapatnekar . 2003. Statistical timing analysis considering spatial correlations using a single PERT-like traversal . In International Conference On Computer Aided Design (ICCAD). 621--625 . H. Chang and S. S. Sapatnekar. 2003. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In International Conference On Computer Aided Design (ICCAD). 621--625."},{"key":"e_1_3_2_1_5_1","unstructured":"C.-K. Cheng J. Lillis S. Lin and N. Chang. 2000. Interconnect analysis and synthesis. Wiley Interscience New York NY.  C.-K. Cheng J. Lillis S. Lin and N. Chang. 2000. Interconnect analysis and synthesis. Wiley Interscience New York NY."},{"key":"e_1_3_2_1_6_1","unstructured":"F. Chollet etal 2015. Keras. https:\/\/keras.io.  F. Chollet et al. 2015. Keras. https:\/\/keras.io."},{"key":"e_1_3_2_1_7_1","volume-title":"IEEE International Test Synthesis Workshop (ITSW).","author":"Davidson S.","year":"1999","unstructured":"S. Davidson . 1999 . Characteristics of the ITC99 benchmark circuits . In IEEE International Test Synthesis Workshop (ITSW). S. Davidson. 1999. Characteristics of the ITC99 benchmark circuits. In IEEE International Test Synthesis Workshop (ITSW)."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1697872"},{"key":"e_1_3_2_1_9_1","first-page":"1","article-title":"A Deep Learning Methodology to Proliferate Golden Signoff Timing","volume":"260","author":"Han S. S.","year":"2014","unstructured":"S. S. Han , A. B. Kahng , S. Nath , and A. S. Vydyanathan . 2014 . A Deep Learning Methodology to Proliferate Golden Signoff Timing . In Design, Automation & Test in Europe (DATE). 260 : 1 -- 260 :6. S. S. Han, A. B. Kahng, S. Nath, and A. S. Vydyanathan. 2014. A Deep Learning Methodology to Proliferate Golden Signoff Timing. In Design, Automation & Test in Europe (DATE). 260:1--260:6.","journal-title":"Design, Automation & Test in Europe (DATE)."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1016\/0893-6080(89)90020-8"},{"key":"e_1_3_2_1_11_1","volume-title":"ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"00","author":"Kahng A. B.","unstructured":"A. B. Kahng , S. Kang , H. Lee , S. Nath , and J. Wadhwani . 2014. Learning-based approximation of interconnect delay and slew in signoff timing tools . In ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP) , Vol. 00 . 1--8. A. B. Kahng, S. Kang, H. Lee, S. Nath, and J. Wadhwani. 2014. Learning-based approximation of interconnect delay and slew in signoff timing tools. In ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP), Vol. 00. 1--8."},{"key":"e_1_3_2_1_12_1","volume-title":"ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP). 1--8.","author":"Kahng A. B.","unstructured":"A. B. Kahng , M. Luo , and S. Nath . 2015. SI for free: machine learning of interconnect coupling delay and transition effects . In ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP). 1--8. A. B. Kahng, M. Luo, and S. Nath. 2015. SI for free: machine learning of interconnect coupling delay and transition effects. In ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP). 1--8."},{"key":"e_1_3_2_1_13_1","unstructured":"J. Knudsen. 2008. Nangate 45nm Open Cell Library. In CDNLive EMEA.  J. Knudsen. 2008. Nangate 45nm Open Cell Library. In CDNLive EMEA."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/1953048.2078195"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.45867"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/13513.13528"}],"event":{"name":"DAC '19: The 56th Annual Design Automation Conference 2019","location":"Las Vegas NV USA","acronym":"DAC '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 56th Annual Design Automation Conference 2019"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3317857","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3316781.3317857","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:53:52Z","timestamp":1750204432000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3317857"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6,2]]},"references-count":16,"alternative-id":["10.1145\/3316781.3317857","10.1145\/3316781"],"URL":"https:\/\/doi.org\/10.1145\/3316781.3317857","relation":{},"subject":[],"published":{"date-parts":[[2019,6,2]]},"assertion":[{"value":"2019-06-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}