{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,6]],"date-time":"2026-01-06T13:38:32Z","timestamp":1767706712084,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,2]],"date-time":"2019-06-02T00:00:00Z","timestamp":1559433600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,2]]},"DOI":"10.1145\/3316781.3317874","type":"proceedings-article","created":{"date-parts":[[2019,5,23]],"date-time":"2019-05-23T18:07:13Z","timestamp":1558634833000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":40,"title":["On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators"],"prefix":"10.1145","author":[{"given":"Haitong","family":"Li","sequence":"first","affiliation":[{"name":"Stanford University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mudit","family":"Bhargava","sequence":"additional","affiliation":[{"name":"Arm Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul N.","family":"Whatmough","sequence":"additional","affiliation":[{"name":"Arm Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.-S. Philip","family":"Wong","sequence":"additional","affiliation":[{"name":"Stanford University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,6,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"e_1_3_2_1_2_1","unstructured":"\"Arm Machine Learning Processor.\" {Online}. Available: https:\/\/developer.arm.com\/products\/processors\/machine-learning\/arm-ml-processor  \"Arm Machine Learning Processor.\" {Online}. Available: https:\/\/developer.arm.com\/products\/processors\/machine-learning\/arm-ml-processor"},{"key":"e_1_3_2_1_3_1","unstructured":"\"NVIDIA Deep Learning Accelerator (NVDLA).\" {Online}. Available: http:\/\/nvdla.org\/primer.html  \"NVIDIA Deep Learning Accelerator (NVDLA).\" {Online}. Available: http:\/\/nvdla.org\/primer.html"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.40"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2015.29"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541967"},{"key":"e_1_3_2_1_7_1","volume-title":"DNN engine: A 28-nm timing-error tolerant sparse deep neural network processor for IoT applications,\" JSSC","author":"Whatmough P. N.","year":"2018","unstructured":"P. N. Whatmough , \" DNN engine: A 28-nm timing-error tolerant sparse deep neural network processor for IoT applications,\" JSSC , 2018 . P. N. Whatmough et al., \"DNN engine: A 28-nm timing-error tolerant sparse deep neural network processor for IoT applications,\" JSSC, 2018."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.30"},{"key":"e_1_3_2_1_9_1","volume-title":"A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications,\" in ISSCC","author":"Clinton M.","year":"2018","unstructured":"M. Clinton , \" A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications,\" in ISSCC , 2018 . M. Clinton et al., \"A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications,\" in ISSCC, 2018."},{"key":"e_1_3_2_1_10_1","volume-title":"A 1Mb 28nm STT-MRAM with 2.8 ns read access time at 1.2 V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination,\" in ISSCC","author":"Dong Q.","year":"2018","unstructured":"Q. Dong , \" A 1Mb 28nm STT-MRAM with 2.8 ns read access time at 1.2 V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination,\" in ISSCC , 2018 . Q. Dong et al., \"A 1Mb 28nm STT-MRAM with 2.8 ns read access time at 1.2 V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination,\" in ISSCC, 2018."},{"key":"e_1_3_2_1_11_1","unstructured":"M. Mendicino \"eMRAM: Winning the IoT and AI Applications.\" {Online}. Available: https:\/\/mramdeveloperday.com\/English\/Conference\/Keynotes.html  M. Mendicino \"eMRAM: Winning the IoT and AI Applications.\" {Online}. Available: https:\/\/mramdeveloperday.com\/English\/Conference\/Keynotes.html"},{"key":"e_1_3_2_1_12_1","volume-title":"Stanford memory trends,\" tech. report","author":"Wong H.-S. P.","year":"2016","unstructured":"H.-S. P. Wong , \" Stanford memory trends,\" tech. report , 2016 . H.-S. P. Wong et al., \"Stanford memory trends,\" tech. report, 2016."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838030"},{"key":"e_1_3_2_1_14_1","volume-title":"High performance 14nm SOI FinFET CMOS technology with 0.0174 μm2 embedded DRAM and 15 levels of Cu metallization,\" in IEDM","author":"Lin C.","year":"2014","unstructured":"C. Lin , \" High performance 14nm SOI FinFET CMOS technology with 0.0174 μm2 embedded DRAM and 15 levels of Cu metallization,\" in IEDM , 2014 . C. Lin et al., \"High performance 14nm SOI FinFET CMOS technology with 0.0174 μm2 embedded DRAM and 15 levels of Cu metallization,\" in IEDM, 2014."},{"key":"e_1_3_2_1_15_1","volume-title":"A high-performance, high-density 28nm eDRAM technology with high-K\/metal-gate,\" in IEDM","author":"Huang K.","year":"2011","unstructured":"K. Huang , \" A high-performance, high-density 28nm eDRAM technology with high-K\/metal-gate,\" in IEDM , 2011 . K. Huang et al., \"A high-performance, high-density 28nm eDRAM technology with high-K\/metal-gate,\" in IEDM, 2011."},{"key":"e_1_3_2_1_16_1","volume-title":"An 800-MHz mixed-VT 4T IFGC embedded DRAM in 28-nm CMOS bulk process for approximate storage applications,\" JSSC","author":"Giterman R.","year":"2018","unstructured":"R. Giterman , \" An 800-MHz mixed-VT 4T IFGC embedded DRAM in 28-nm CMOS bulk process for approximate storage applications,\" JSSC , 2018 . R. Giterman et al., \"An 800-MHz mixed-VT 4T IFGC embedded DRAM in 28-nm CMOS bulk process for approximate storage applications,\" JSSC, 2018."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.13"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.12"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847276"},{"key":"e_1_3_2_1_21_1","volume-title":"SCALE-Sim: Systolic CNN accelerator,\" arXiv preprint arXiv:1811.02883","author":"Samajdar A.","year":"2018","unstructured":"A. Samajdar , \" SCALE-Sim: Systolic CNN accelerator,\" arXiv preprint arXiv:1811.02883 , 2018 . A. Samajdar et al., \"SCALE-Sim: Systolic CNN accelerator,\" arXiv preprint arXiv:1811.02883, 2018."},{"key":"e_1_3_2_1_22_1","unstructured":"I. Bratt \"Arm's First-Generation Machine Learning Processor \" Hot Chips 2018. {Online}. Available: https:\/\/www.hotchips.org\/hc30\/2conf\/2.07_ARM_ML_Processor_HC30_ARM_2018_08_17.pdf  I. Bratt \"Arm's First-Generation Machine Learning Processor \" Hot Chips 2018. {Online}. Available: https:\/\/www.hotchips.org\/hc30\/2conf\/2.07_ARM_ML_Processor_HC30_ARM_2018_08_17.pdf"},{"key":"e_1_3_2_1_23_1","volume-title":"Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond,\" in IEDM","author":"Park C.","year":"2015","unstructured":"C. Park , \" Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond,\" in IEDM , 2015 . C. Park et al., \"Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond,\" in IEDM, 2015."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037702"},{"key":"e_1_3_2_1_25_1","volume-title":"43pJ\/cycle non-volatile microcontroller with 4.7 μs shutdown\/wake-up integrating 2.3-bit\/cell resistive RAM and resilience techniques,\" in ISSCC","author":"Wu T. F.","year":"2019","unstructured":"T. F. Wu , \" 43pJ\/cycle non-volatile microcontroller with 4.7 μs shutdown\/wake-up integrating 2.3-bit\/cell resistive RAM and resilience techniques,\" in ISSCC , 2019 . T. F. Wu et al., \"43pJ\/cycle non-volatile microcontroller with 4.7 μs shutdown\/wake-up integrating 2.3-bit\/cell resistive RAM and resilience techniques,\" in ISSCC, 2019."}],"event":{"name":"DAC '19: The 56th Annual Design Automation Conference 2019","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Las Vegas NV USA","acronym":"DAC '19"},"container-title":["Proceedings of the 56th Annual Design Automation Conference 2019"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3317874","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3316781.3317874","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:53:53Z","timestamp":1750204433000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3317874"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6,2]]},"references-count":25,"alternative-id":["10.1145\/3316781.3317874","10.1145\/3316781"],"URL":"https:\/\/doi.org\/10.1145\/3316781.3317874","relation":{},"subject":[],"published":{"date-parts":[[2019,6,2]]},"assertion":[{"value":"2019-06-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}