{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:08:43Z","timestamp":1767262123381,"version":"3.41.0"},"reference-count":61,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2019,7,8]],"date-time":"2019-07-08T00:00:00Z","timestamp":1562544000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"BPI","award":["ES3CAP"],"award-info":[{"award-number":["ES3CAP"]}]},{"DOI":"10.13039\/501100009077","name":"ITEA3","doi-asserted-by":"publisher","award":["14014 ASSUME"],"award-info":[{"award-number":["14014 ASSUME"]}],"id":[{"id":"10.13039\/501100009077","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2019,9,30]]},"abstract":"<jats:p>We present the first end-to-end modeling and compilation flow to parallelize hard real-time control applications while fully guaranteeing the respect of real-time requirements on off-the-shelf hardware. It scales to thousands of dataflow nodes and has been validated on two production avionics applications. Unlike classical optimizing compilation, it takes as input non-functional requirements (real time, resource limits). To enforce these requirements, the compiler follows a static resource allocation strategy, from coarse-grain tasks communicating over an interconnection network all the way to individual variables and memory accesses. It controls timing interferences resulting from mapping decisions in a precise, safe, and scalable way.<\/jats:p>","DOI":"10.1145\/3328799","type":"journal-article","created":{"date-parts":[[2019,7,9]],"date-time":"2019-07-09T12:45:29Z","timestamp":1562676329000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Correct-by-Construction Parallelization of Hard Real-Time Avionics Applications on Off-the-Shelf Predictable Hardware"],"prefix":"10.1145","volume":"16","author":[{"given":"Keryan","family":"Didier","sequence":"first","affiliation":[{"name":"Inria, France"}]},{"given":"Dumitru","family":"Potop-Butucaru","sequence":"additional","affiliation":[{"name":"Inria, France"}]},{"given":"Guillaume","family":"Iooss","sequence":"additional","affiliation":[{"name":"Inria and ENS, France"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8866-5343","authenticated-orcid":false,"given":"Albert","family":"Cohen","sequence":"additional","affiliation":[{"name":"Inria and ENS, France"}]},{"given":"Jean","family":"Souyris","sequence":"additional","affiliation":[{"name":"Airbus, France"}]},{"given":"Philippe","family":"Baufreton","sequence":"additional","affiliation":[{"name":"Safran, France"}]},{"given":"Amaury","family":"Graillat","sequence":"additional","affiliation":[{"name":"Kalray and Universit\u00e9 Grenoble-Alpes, France"}]}],"member":"320","published-online":{"date-parts":[[2019,7,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/212094.212131"},{"key":"e_1_2_1_2_1","unstructured":"ARINC653. 2010. ARINC 653: Avionics Application Software Standard Interface. Part 1 -- Required Services. Revision 3.  ARINC653. 2010. ARINC 653: Avionics Application Software Standard Interface. Part 1 -- Required Services. Revision 3."},{"key":"e_1_2_1_3_1","volume-title":"X. Raynaud, and R. Sirdey.","author":"Aubry P.","year":"2013","unstructured":"P. Aubry , P.-E. Beaucamps , F. Blanc , B. Bodin , S. Carpov , L. Cudennec , V. David , P. Dore , P. Dubrulle , B. Dupont de Dinechin , F. Galea , T. Goubier , M. Harrand , S. Jones , J.-D. Lesage , S. Louise , N. Morey Chaisemartin , Thanh Hai Nguyen , X. Raynaud, and R. Sirdey. 2013 . Extended cyclostatic dataflow program compilation and execution for an integrated manycore processor. In Proceedings ICCS. P. Aubry, P.-E. Beaucamps, F. Blanc, B. Bodin, S. Carpov, L. Cudennec, V. David, P. Dore, P. Dubrulle, B. Dupont de Dinechin, F. Galea, T. Goubier, M. Harrand, S. Jones, J.-D. Lesage, S. Louise, N. Morey Chaisemartin, Thanh Hai Nguyen, X. Raynaud, and R. Sirdey. 2013. Extended cyclostatic dataflow program compilation and execution for an integrated manycore processor. In Proceedings ICCS."},{"key":"e_1_2_1_4_1","unstructured":"autosar {n.d.}. AUTOSAR. Retrieved March 20 2018 from autosar.org.  autosar {n.d.}. AUTOSAR. Retrieved March 20 2018 from autosar.org."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.655185"},{"key":"e_1_2_1_6_1","doi-asserted-by":"crossref","unstructured":"S. Baruah M. Bertogna and G. Buttazzo. 2015. Multiprocessor Scheduling for Real-Time Systems. Springer.   S. Baruah M. Bertogna and G. Buttazzo. 2015. Multiprocessor Scheduling for Real-Time Systems. Springer.","DOI":"10.1007\/978-3-319-08696-5"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MS.2011.27"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1375657.1375674"},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"B. Bodin A. Munier Kordon and B. Dupont de Dinechin. 2012. K-periodic schedules for evaluating the maximum throughput of a synchronous dataflow graph. In SAMOS XII.  B. Bodin A. Munier Kordon and B. Dupont de Dinechin. 2012. K-periodic schedules for evaluating the maximum throughput of a synchronous dataflow graph. In SAMOS XII.","DOI":"10.1109\/SAMOS.2012.6404169"},{"volume-title":"Proceedings ERTS.","author":"Brocal V.","key":"e_1_2_1_11_1","unstructured":"V. Brocal , M. Masmano , I. Ripoll , A. Crespo , P. Balbastre , and J. J. Metge . 2010. Xoncrete: A scheduling tool for partitioned real-time systems . In Proceedings ERTS. V. Brocal, M. Masmano, I. Ripoll, A. Crespo, P. Balbastre, and J. J. Metge. 2010. Xoncrete: A scheduling tool for partitioned real-time systems. In Proceedings ERTS."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2014.19"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2579676"},{"key":"e_1_2_1_14_1","article-title":"From dataflow specification to multiprocessor partitioned time-triggered real-time implementation","volume":"2","author":"Carle T.","year":"2015","unstructured":"T. Carle , D. Potop-Butucaru , Y. Sorel , and D. Lesens . 2015 . From dataflow specification to multiprocessor partitioned time-triggered real-time implementation . Leibniz Trans. Embedded Syst. 2 , 2 (2015), 01:1--01:30. T. Carle, D. Potop-Butucaru, Y. Sorel, and D. Lesens. 2015. From dataflow specification to multiprocessor partitioned time-triggered real-time implementation. Leibniz Trans. Embedded Syst. 2, 2 (2015), 01:1--01:30.","journal-title":"Leibniz Trans. Embedded Syst."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/780732.780754"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/41625.41641"},{"key":"e_1_2_1_17_1","doi-asserted-by":"crossref","unstructured":"M. Chetto (Ed.). 2014. Real-time Systems Scheduling Volumes 1 and 2. ISTE Ltd. and John Wiley 8 Sons Inc.  M. Chetto (Ed.). 2014. Real-time Systems Scheduling Volumes 1 and 2. ISTE Ltd. and John Wiley 8 Sons Inc.","DOI":"10.1002\/9781119042976.ch1"},{"volume-title":"Proceedings ERTS2","author":"Cohen A.","key":"e_1_2_1_18_1","unstructured":"A. Cohen , V. Perrelle , D. Potop-Butucaru , M. Pouzet , E. Soubiran , and Z. Zhang . 2016. Hard real time and mixed time criticality on off-the-shelf embedded multi-cores . In Proceedings ERTS2 , Toulouse, France. A. Cohen, V. Perrelle, D. Potop-Butucaru, M. Pouzet, E. Soubiran, and Z. Zhang. 2016. Hard real time and mixed time criticality on off-the-shelf embedded multi-cores. In Proceedings ERTS2, Toulouse, France."},{"volume-title":"Proceedings FDL","author":"Cola\u00e7o J.-L.","key":"e_1_2_1_19_1","unstructured":"J.-L. Cola\u00e7o , B. Pagano , C. Pasteur , and M. Pouzet . 2018. Scade 6: From a Kahn semantics to a Kahn implementation for multicore . In Proceedings FDL . Munich, Germany. J.-L. Cola\u00e7o, B. Pagano, C. Pasteur, and M. Pouzet. 2018. Scade 6: From a Kahn semantics to a Kahn implementation for multicore. In Proceedings FDL. Munich, Germany."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-015-9244-x"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/115372.115320"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2735960.2735972"},{"volume-title":"Proceedings SETTA. LNCS 10606","author":"Deutschbein C.","key":"e_1_2_1_23_1","unstructured":"C. Deutschbein , T. Fleming , A. Burns , and S. Baruah . 2017. Multi-core cyclic executives for safety-critical systems . In Proceedings SETTA. LNCS 10606 . C. Deutschbein, T. Fleming, A. Burns, and S. Baruah. 2017. Multi-core cyclic executives for safety-critical systems. In Proceedings SETTA. LNCS 10606."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2248418.2248426"},{"key":"e_1_2_1_25_1","doi-asserted-by":"crossref","unstructured":"K. Goossens M. Koedam A. Nelson S. Sinha S. Goossens Yonghui Li G. Breaban R. van Kampenhout R. Tavakoli J. Valencia H. A. Balef B. Akesson S. Stuijk M. Geilen Dip Goswami and M. Nabi. 2017. NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications. Springer Netherlands Dordrecht 1--40.  K. Goossens M. Koedam A. Nelson S. Sinha S. Goossens Yonghui Li G. Breaban R. van Kampenhout R. Tavakoli J. Valencia H. A. Balef B. Akesson S. Stuijk M. Geilen Dip Goswami and M. Nabi. 2017. NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications. Springer Netherlands Dordrecht 1--40.","DOI":"10.1007\/978-94-017-7358-4_17-1"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-22975-1_8"},{"volume-title":"Proceedings DATE.","author":"Graillat A.","key":"e_1_2_1_27_1","unstructured":"A. Graillat , M. Moy , P. Raymond , and B. Dupont de Dinechin. 2018. Parallel code generation of synchronous programs for a many-core architecture . In Proceedings DATE. A. Graillat, M. Moy, P. Raymond, and B. Dupont de Dinechin. 2018. Parallel code generation of synchronous programs for a many-core architecture. In Proceedings DATE."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2005.1487884"},{"volume-title":"The Heptagon\/BZR distribution. Retrieved","year":"2018","key":"e_1_2_1_29_1","unstructured":"heptagon {n.d.}. The Heptagon\/BZR distribution. Retrieved May 19, 2018 from http:\/\/heptagon.gforge.inria.fr\/. heptagon {n.d.}. The Heptagon\/BZR distribution. Retrieved May 19, 2018 from http:\/\/heptagon.gforge.inria.fr\/."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.730530"},{"key":"e_1_2_1_31_1","unstructured":"Infineon {n.d.}. AURIX\u2122 TC27x D-Step User\u2019s Manual. Infineon. V2.2 2014-12.  Infineon {n.d.}. AURIX\u2122 TC27x D-Step User\u2019s Manual. Infineon. V2.2 2014-12."},{"key":"e_1_2_1_32_1","volume-title":"Intel. Retrieved","author":"Intel","year":"2010","unstructured":"Intel 2010 . Detecting Memory Bandwidth Saturation in Threaded Applications . Intel. Retrieved May 22, 2018 from https:\/\/software.intel.com\/en-us\/articles\/detecting-memory-bandwidth-saturation-in-threaded-applications\/. Intel 2010. Detecting Memory Bandwidth Saturation in Threaded Applications. Intel. Retrieved May 22, 2018 from https:\/\/software.intel.com\/en-us\/articles\/detecting-memory-bandwidth-saturation-in-threaded-applications\/."},{"key":"e_1_2_1_33_1","unstructured":"Kalray S. A. 2016. MPPA\u00ae-256 Bostan Cluster and I\/O Subsystem Architecture. Kalray S.A.  Kalray S. A. 2016. MPPA\u00ae-256 Bostan Cluster and I\/O Subsystem Architecture. Kalray S.A."},{"key":"e_1_2_1_34_1","unstructured":"labview {n.d.}. LabView. Retrieved March 20 2018 from ni.com\/labview.  labview {n.d.}. LabView. Retrieved March 20 2018 from ni.com\/labview."},{"volume-title":"2012 LLVM Developers\u2019 Meeting presentation.","author":"Larin S.","key":"e_1_2_1_35_1","unstructured":"S. Larin and A. Trick . 2012. Instruction scheduling for Superscalar and VLIW platforms. Temporal perspective. https:\/\/llvm.org\/devmtg\/2012-11\/Larin-Trick-Scheduling.pdf . 2012 LLVM Developers\u2019 Meeting presentation. S. Larin and A. Trick. 2012. Instruction scheduling for Superscalar and VLIW platforms. Temporal perspective. https:\/\/llvm.org\/devmtg\/2012-11\/Larin-Trick-Scheduling.pdf. 2012 LLVM Developers\u2019 Meeting presentation."},{"key":"e_1_2_1_36_1","volume-title":"1994 Proceedings of the 27th Hawaii International Conference on System Sciences","volume":"1","author":"Liao G.","unstructured":"G. Liao , E. R. Altman , V. K. Agarwal , and G. R. Gao . 1994. A comparative study of multiprocessor list scheduling heuristics . In 1994 Proceedings of the 27th Hawaii International Conference on System Sciences , Vol. 1 . 68--77. G. Liao, E. R. Altman, V. K. Agarwal, and G. R. Gao. 1994. A comparative study of multiprocessor list scheduling heuristics. In 1994 Proceedings of the 27th Hawaii International Conference on System Sciences, Vol. 1. 68--77."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/HASE.2011.38"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.5555\/1416222.1416271"},{"volume-title":"Advanced Compiler Design and Implementation","author":"Muchnick S.","key":"e_1_2_1_39_1","unstructured":"S. Muchnick . 1997. Advanced Compiler Design and Implementation . Academic Press . S. Muchnick. 1997. Advanced Compiler Design and Implementation. Academic Press."},{"volume-title":"Proceedings of the WCET workshop","author":"Ozaktas H.","key":"e_1_2_1_40_1","unstructured":"H. Ozaktas , C. Rochange , and P. Sainrat . 2013. Automatic WCET analysis of real-time parallel applications . In Proceedings of the WCET workshop . Paris, France. https:\/\/hal.archives-ouvertes.fr\/hal-01239727. H. Ozaktas, C. Rochange, and P. Sainrat. 2013. Automatic WCET analysis of real-time parallel applications. In Proceedings of the WCET workshop. Paris, France. https:\/\/hal.archives-ouvertes.fr\/hal-01239727."},{"volume-title":"Proceedings ERTS2","author":"Pagano B.","key":"e_1_2_1_41_1","unstructured":"B. Pagano , C. Pasteur , G. Siegel , and R. Knizek . 2018. A model based safety critical flow for the AURIX\u2122 multi-core platform . In Proceedings ERTS2 . Toulouse, France. B. Pagano, C. Pasteur, G. Siegel, and R. Knizek. 2018. A model based safety critical flow for the AURIX\u2122 multi-core platform. In Proceedings ERTS2. Toulouse, France."},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10626-011-0107-x"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/3273905.3273907"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2011.33"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2997465.2997496"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629335.1629356"},{"volume-title":"Proceedings WCET","author":"Potop-Butucaru D.","key":"e_1_2_1_47_1","unstructured":"D. Potop-Butucaru and I. Puaut . 2013. Integrated worst-case execution time estimation of multicore applications . In Proceedings WCET . Paris, France. D. Potop-Butucaru and I. Puaut. 2013. Integrated worst-case execution time estimation of multicore applications. In Proceedings WCET. Paris, France."},{"volume-title":"Proceedings of the 14th Annual Workshop on Microprogramming, IEEE.","author":"Rau B. R.","key":"e_1_2_1_48_1","unstructured":"B. R. Rau and C. D. Glaeser . 1981. Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing . In Proceedings of the 14th Annual Workshop on Microprogramming, IEEE. B. R. Rau and C. D. Glaeser. 1981. Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. In Proceedings of the 14th Annual Workshop on Microprogramming, IEEE."},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/2997465.2997472"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126496"},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/1017753.1017795"},{"key":"e_1_2_1_52_1","volume-title":"SchedMCore toolset. Retrieved","author":"Core","year":"2017","unstructured":"SchedM Core {n.d.}. SchedMCore toolset. Retrieved June 2017 from sites.onera.fr\/schedmcore\/. SchedMCore {n.d.}. SchedMCore toolset. Retrieved June 2017 from sites.onera.fr\/schedmcore\/."},{"volume-title":"Proceedings DATE.","author":"Skalistis S.","key":"e_1_2_1_53_1","unstructured":"S. Skalistis and A. Simalatsar . 2017. Near-optimal deployment of dataflow applications on many-core platforms with real-time guarantees . In Proceedings DATE. S. Skalistis and A. Simalatsar. 2017. Near-optimal deployment of dataflow applications on many-core platforms with real-time guarantees. In Proceedings DATE."},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/123465.123482"},{"key":"e_1_2_1_55_1","volume-title":"SynDEx mapping tool. Retrieved","author":"Syndex","year":"2017","unstructured":"Syndex {n.d.}. SynDEx mapping tool. Retrieved June 2017 from www.syndex.org. Syndex {n.d.}. SynDEx mapping tool. Retrieved June 2017 from www.syndex.org."},{"key":"e_1_2_1_56_1","unstructured":"sysml {n.d.}. SysML. Retrieved March 20 2018 from http:\/\/www.omgsysml.org\/.  sysml {n.d.}. SysML. Retrieved March 20 2018 from http:\/\/www.omgsysml.org\/."},{"key":"e_1_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/79173.79181"},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347389"},{"key":"e_1_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/2500886"},{"key":"e_1_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2013287"},{"volume-title":"Proceedings MCSoC.","author":"Yip E.","key":"e_1_2_1_61_1","unstructured":"E. Yip , A. Girault , P. Roop , and M. Biglari-Abhari . 2016. The ForeC synchronous deterministic parallel programming language for multicores . In Proceedings MCSoC. E. Yip, A. Girault, P. Roop, and M. Biglari-Abhari. 2016. The ForeC synchronous deterministic parallel programming language for multicores. In Proceedings MCSoC."},{"volume-title":"Proceedings RTAS.","author":"Zimmer M.","key":"e_1_2_1_62_1","unstructured":"M. Zimmer , D. Broman , C. Shaver , and E. A. Lee . 2014. FlexPRET: A processor platform for mixed-criticality systems . In Proceedings RTAS. M. Zimmer, D. Broman, C. Shaver, and E. A. Lee. 2014. FlexPRET: A processor platform for mixed-criticality systems. In Proceedings RTAS."}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3328799","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3328799","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:33:03Z","timestamp":1750199583000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3328799"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7,8]]},"references-count":61,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2019,9,30]]}},"alternative-id":["10.1145\/3328799"],"URL":"https:\/\/doi.org\/10.1145\/3328799","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2019,7,8]]},"assertion":[{"value":"2018-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2019-07-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}