{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:29:37Z","timestamp":1750220977265,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":48,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,2,19]],"date-time":"2020-02-19T00:00:00Z","timestamp":1582070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Natural Science Foundation of China","award":["61925206"],"award-info":[{"award-number":["61925206"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,2,19]]},"DOI":"10.1145\/3332466.3374535","type":"proceedings-article","created":{"date-parts":[[2020,2,19]],"date-time":"2020-02-19T19:13:53Z","timestamp":1582139633000},"page":"348-361","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["No barrier in the road"],"prefix":"10.1145","author":[{"given":"Nian","family":"Liu","sequence":"first","affiliation":[{"name":"Shanghai Jiao Tong University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Binyu","family":"Zang","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haibo","family":"Chen","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,2,19]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"ARM AMBA. 2011. AXI and ACE Protocol Specification.  ARM AMBA. 2011. AXI and ACE Protocol Specification."},{"volume-title":"Architecture Reference Manual. ARMv8, for ARMv8-A architecture profile","year":"2018","author":"ARM ARM.","key":"e_1_3_2_1_2_1"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCS.2018.00068"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2688500.2688503"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2851141.2851166"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2829952"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1353522.1353528"},{"key":"e_1_3_2_1_9_1","unstructured":"Jonathan Corbet. 2014. MCS locks and qspinlocks. https:\/\/lwn.net\/Articles\/590243\/.  Jonathan Corbet. 2014. MCS locks and qspinlocks. https:\/\/lwn.net\/Articles\/590243\/."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1989493.1989502"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2686884"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2009.64"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1989493.1989549"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145816.2145849"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168877"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2688500.2688501"},{"key":"e_1_3_2_1_17_1","unstructured":"SD Hammond C Hughes MJ Levenhagen CT Vaughan AJ Younge B Schwaller MJ Aguilar KT Pedretti and JH Laros. [n. d.]. Evaluating the Marvell ThunderX2 Server Processor for HPC Workloads ([n. d.]).  SD Hammond C Hughes MJ Levenhagen CT Vaughan AJ Younge B Schwaller MJ Aguilar KT Pedretti and JH Laros. [n. d.]. Evaluating the Marvell ThunderX2 Server Processor for HPC Workloads ([n. d.])."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1810479.1810540"},{"key":"e_1_3_2_1_19_1","unstructured":"Arm Holdings [n. d.]. ARM Cortex-A Series Programmer's Guide for ARMv8.  Arm Holdings [n. d.]. ARM Cortex-A Series Programmer's Guide for ARMv8."},{"volume-title":"The SPARC architecture manual","author":"International Inc SPARC","key":"e_1_3_2_1_20_1"},{"volume-title":"The Intel\u00ae 64 and IA-32 architectures software developer's manual","author":"Intel Intel","key":"e_1_3_2_1_21_1"},{"key":"e_1_3_2_1_22_1","unstructured":"Data Center Knowledge. 2015. PayPal Deploys ARM Servers in Data Centers.  Data Center Knowledge. 2015. PayPal Deploys ARM Servers in Data Centers."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2809808"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.14"},{"volume-title":"2012 USENIX Annual Technical Conference","year":"2012","author":"Lozi Jean-Pierre","key":"e_1_3_2_1_25_1"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2845079"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1007\/11823285_84"},{"volume-title":"A tutorial introduction to the ARM and POWER relaxed memory models. Draft available from http:\/\/www.cl.cam.ac.uk\/~pes20\/ppc-supplemental\/test7.pdf","year":"2012","author":"Maranget Luc","key":"e_1_3_2_1_28_1"},{"volume-title":"Memory barriers: a hardware view for software hackers","year":"2010","author":"McKenney Paul E","key":"e_1_3_2_1_29_1"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/103727.103729"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3033019.3033021"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2980987"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/3276506"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-03359-9_27"},{"key":"e_1_3_2_1_35_1","volume-title":"Proceedings of the International Workshop on Parallel and Distributed Computing for Symbolic and Irregular Applications","volume":"16","author":"Oyama Yoshihiro","year":"1999"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3158107"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/E2SC.2016.008"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503281"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503281"},{"key":"e_1_3_2_1_40_1","unstructured":"J Rath. 2013. Baidu deploys marvell armbased cloud server.  J Rath. 2013. Baidu deploys marvell armbased cloud server."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2851141.2851150"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/3132747.3132771"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993520"},{"volume-title":"Proceedings of the 24th High Performance Computing Symposium, Pasadena, HPC 2016, part of the 2016 Spring Simulation Multi-conference, SpringSim '16","year":"2016","author":"Selinger Andreas","key":"e_1_3_2_1_44_1"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1785414.1785443"},{"volume-title":"The AMD Opteron A1100 Processor Codenamed \"Seattle","author":"White Sean","key":"e_1_3_2_1_46_1"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-019-02911-9"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/2851141.2851176"}],"event":{"name":"PPoPP '20: 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGHPC ACM Special Interest Group on High Performance Computing, Special Interest Group on High Performance Computing"],"location":"San Diego California","acronym":"PPoPP '20"},"container-title":["Proceedings of the 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3332466.3374535","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3332466.3374535","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:54:38Z","timestamp":1750204478000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3332466.3374535"}},"subtitle":["a comprehensive study and optimization of ARM barriers"],"short-title":[],"issued":{"date-parts":[[2020,2,19]]},"references-count":48,"alternative-id":["10.1145\/3332466.3374535","10.1145\/3332466"],"URL":"https:\/\/doi.org\/10.1145\/3332466.3374535","relation":{},"subject":[],"published":{"date-parts":[[2020,2,19]]},"assertion":[{"value":"2020-02-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}