{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T11:20:21Z","timestamp":1764588021435,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,8,5]],"date-time":"2019-08-05T00:00:00Z","timestamp":1564963200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,8,5]]},"DOI":"10.1145\/3337821.3337877","type":"proceedings-article","created":{"date-parts":[[2019,7,25]],"date-time":"2019-07-25T12:34:36Z","timestamp":1564058076000},"page":"1-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Express Link Placement for NoC-Based Many-Core Platforms"],"prefix":"10.1145","author":[{"given":"Yunfan","family":"Li","sequence":"first","affiliation":[{"name":"School of Electrical Engineering and Computer Science, Oregon State University, United States"}]},{"given":"Di","family":"Zhu","sequence":"additional","affiliation":[{"name":"Ming Hsieh Department of Electrical and Computer Engineering, University of Southern California, United States"}]},{"given":"Lizhong","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering and Computer Science, Oregon State University, United States"}]}],"member":"320","published-online":{"date-parts":[[2019,8,5]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","unstructured":"Agarwal N. Krishna T. Peh L. S. & Jha N. K. (2009 April). \"GARNET: A detailed on-chip network model inside a full-system simulator \" International Symposium on Performance Analysis of Systems and Software (ISPASS) 33--42.  Agarwal N. Krishna T. Peh L. S. & Jha N. K. (2009 April). \"GARNET: A detailed on-chip network model inside a full-system simulator \" International Symposium on Performance Analysis of Systems and Software (ISPASS) 33--42.","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629435.1629453"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_5_1","volume-title":"CMP network-on-chip overlaid with multi-band RF-interconnect,\" High Performance Computer Architecture","author":"Chang M. F.","year":"2008","unstructured":"Chang , M. F. , ( 2008 ) \" CMP network-on-chip overlaid with multi-band RF-interconnect,\" High Performance Computer Architecture (HPCA) IEEE 14th International Symposium on. Chang, M. F., et al. (2008) \"CMP network-on-chip overlaid with multi-band RF-interconnect,\" High Performance Computer Architecture (HPCA) IEEE 14th International Symposium on."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.26"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.33"},{"key":"e_1_3_2_1_8_1","volume-title":"Introduction to algorithms,\" MIT press","author":"Cormen C. E.","year":"2001","unstructured":"T. H. Cormen , C. E. Leiserson , R. L. Rivest , and C. Stein , \" Introduction to algorithms,\" MIT press , 2001 . T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, \"Introduction to algorithms,\" MIT press, 2001."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.83652"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/2821589"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665680"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2004592"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/1320302.1320836"},{"key":"e_1_3_2_1_14_1","volume-title":"Express cube topologies for on-chip interconnects,\" In 15th IEEE International Symposium on High Performance Computer Architecture (HPCA), 163--174","author":"Grot B.","year":"2009","unstructured":"Grot , B. , Hestness , J. , Keckler , S. W. , & Mutlu , O. ( 2009 ). \" Express cube topologies for on-chip interconnects,\" In 15th IEEE International Symposium on High Performance Computer Architecture (HPCA), 163--174 . Grot, B., Hestness, J., Keckler, S. W., & Mutlu, O. (2009). \"Express cube topologies for on-chip interconnects,\" In 15th IEEE International Symposium on High Performance Computer Architecture (HPCA), 163--174."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2006.15"},{"key":"e_1_3_2_1_16_1","volume-title":"A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS,\" In Proceedings of the International Solid-State Circuits Conference (ISSCC)","author":"Howard J.","year":"2010","unstructured":"Howard , J. , ( 2010 ). \" A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS,\" In Proceedings of the International Solid-State Circuits Conference (ISSCC) . Howard, J., et al. (2010). \"A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS,\" In Proceedings of the International Solid-State Circuits Conference (ISSCC)."},{"key":"e_1_3_2_1_17_1","volume-title":"Equalized interconnects for on-chip networks: modeling and optimization framework,\" In Int'l Conference Computer-Aided Design (ICCAD), 552--559","author":"Kim B.","year":"2007","unstructured":"Kim , B. and Stojanovi\u0107 , V . ( 2007 ). \" Equalized interconnects for on-chip networks: modeling and optimization framework,\" In Int'l Conference Computer-Aided Design (ICCAD), 552--559 . Kim, B. and Stojanovi\u0107, V. (2007). \"Equalized interconnects for on-chip networks: modeling and optimization framework,\" In Int'l Conference Computer-Aided Design (ICCAD), 552--559."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.15"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250681"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169049"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228431"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"crossref","unstructured":"S. Vangal et al. (2007). \"An 80-tile 1.28 TFLOPS network-on-chip in 65nm CMOS \" In International Solid-State Circuits Conference (ISSCC).  S. Vangal et al. (2007). \"An 80-tile 1.28 TFLOPS network-on-chip in 65nm CMOS \" In International Solid-State Circuits Conference (ISSCC).","DOI":"10.1109\/ISSCC.2007.373606"}],"event":{"name":"ICPP 2019: 48th International Conference on Parallel Processing","sponsor":["University of Tsukuba University of Tsukuba"],"location":"Kyoto Japan","acronym":"ICPP 2019"},"container-title":["Proceedings of the 48th International Conference on Parallel Processing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3337821.3337877","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3337821.3337877","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:54:26Z","timestamp":1750204466000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3337821.3337877"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,8,5]]},"references-count":24,"alternative-id":["10.1145\/3337821.3337877","10.1145\/3337821"],"URL":"https:\/\/doi.org\/10.1145\/3337821.3337877","relation":{},"subject":[],"published":{"date-parts":[[2019,8,5]]},"assertion":[{"value":"2019-08-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}