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Archit. Code Optim."],"published-print":{"date-parts":[[2019,9,30]]},"abstract":"<jats:p>DRAM caches have emerged as an efficient new layer in the memory hierarchy to address the increasing diversity of memory components. When a small amount of fast memory is combined with slow but large memory, the cache-based organization of the fast memory can provide a SW-transparent solution for the hybrid memory systems. In such DRAM cache designs, their effectiveness is affected by the bandwidth and latency of both fast and slow memory. To quantitatively assess the effect of memory configurations and application patterns on the DRAM cache designs, this article first investigates how three prior approaches perform with six hybrid memory scenarios. From the investigation, we observe no single DRAM cache organization always outperforms the other organizations across the diverse hybrid memory configurations and memory access patterns. Based on this observation, this article proposes a reconfigurable DRAM cache design that can adapt to different hybrid memory combinations and workload patterns. Unlike the fixed tag and data arrays of conventional on-chip SRAM caches, this study advocates to exploit the flexibility of DRAM caches, which can store tags and data to DRAM in any arbitrary way. Using a sample-based mechanism, the proposed DRAM cache controller dynamically finds the best organization from three candidates and applies the best one by reconfiguring the tags and data layout in the DRAM cache. Our evaluation shows that the proposed morphable DRAM cache can outperform the fixed DRAM configurations across six hybrid memory configurations.<\/jats:p>","DOI":"10.1145\/3338505","type":"journal-article","created":{"date-parts":[[2019,7,19]],"date-time":"2019-07-19T13:17:14Z","timestamp":1563542234000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Morphable DRAM Cache Design for Hybrid Memory Systems"],"prefix":"10.1145","volume":"16","author":[{"given":"Sanghoon","family":"Cha","sequence":"first","affiliation":[{"name":"KAIST, Daejeon, Republic of Korea"}]},{"given":"Bokyeong","family":"Kim","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Republic of Korea"}]},{"given":"Chang Hyun","family":"Park","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Republic of Korea"}]},{"given":"Jaehyuk","family":"Huh","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Republic of Korea"}]}],"member":"320","published-online":{"date-parts":[[2019,7,18]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037706"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430554"},{"key":"e_1_2_1_3_1","unstructured":"Mike Amidi. 2016. NVDIMM-X deliver DRAM performance at NAND capacity (Flash Memory Summit\u201916).  Mike Amidi. 2016. NVDIMM-X deliver DRAM performance at NAND capacity (Flash Memory Summit\u201916)."},{"key":"e_1_2_1_4_1","volume-title":"IEEE International Solid - State Circuits Conference (ISSCC\u201918)","author":"Cheong W.","unstructured":"W. Cheong , C. Yoon , S. Woo , K. Han , D. Kim , C. Lee , Y. Choi , S. Kim , D. Kang , G. Yu , J. Kim , J. Park , K. Song , K. Park , S. Cho , H. Oh , D. D. G. Lee , J. Choi , and J. Jeong . 2018. A flash memory controller for 15s ultra-low-latency SSD using high-speed 3D NAND flash with 3s read time . In IEEE International Solid - State Circuits Conference (ISSCC\u201918) . 338--340. W. Cheong, C. Yoon, S. Woo, K. Han, D. Kim, C. Lee, Y. Choi, S. Kim, D. Kang, G. Yu, J. Kim, J. Park, K. Song, K. Park, S. Cho, H. Oh, D. D. G. Lee, J. Choi, and J. Jeong. 2018. A flash memory controller for 15s ultra-low-latency SSD using high-speed 3D NAND flash with 3s read time. In IEEE International Solid - State Circuits Conference (ISSCC\u201918). 338--340."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.63"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750387"},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-49)","author":"Chou Chiachen","unstructured":"Chiachen Chou , Aamer Jaleel , and Moinuddin K. Qureshi . 2016. CANDY: Enabling coherent DRAM caches for multi-node systems . In Proceedings of the 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-49) . 1--13. Chiachen Chou, Aamer Jaleel, and Moinuddin K. Qureshi. 2016. CANDY: Enabling coherent DRAM caches for multi-node systems. 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