{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T18:17:43Z","timestamp":1759342663123,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":66,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,22]],"date-time":"2019-06-22T00:00:00Z","timestamp":1561161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,22]]},"DOI":"10.1145\/3338698.3338893","type":"proceedings-article","created":{"date-parts":[[2019,7,25]],"date-time":"2019-07-25T12:34:36Z","timestamp":1564058076000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Teaching Heterogeneous Computing with System-Level Design Methods"],"prefix":"10.1145","author":[{"given":"Luca P.","family":"Carloni","sequence":"first","affiliation":[{"name":"Department of Computer Science, Columbia University in the City of New York, New York, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emilio G.","family":"Cota","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Columbia University in the City of New York, New York, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giuseppe Di","family":"Guglielmo","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Columbia University in the City of New York, New York, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davide","family":"Giri","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Columbia University in the City of New York, New York, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jihye","family":"Kwon","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Columbia University in the City of New York, New York, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Mantovani","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Columbia University in the City of New York, New York, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Piccolboni","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Columbia University in the City of New York, New York, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michele","family":"Petracca","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Columbia University in the City of New York, New York, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2019,6,22]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"ECE 425. 2019. Introduction to VLSI System Design. https:\/\/courses.engr.illinois.edu\/ece425\/sp2019\/lectures.html.  ECE 425. 2019. Introduction to VLSI System Design. https:\/\/courses.engr.illinois.edu\/ece425\/sp2019\/lectures.html."},{"key":"e_1_3_2_1_2_1","unstructured":"ELEC 522. 2018. Advanced VLSI Design. https:\/\/www.clear.rice.edu\/elec522\/.  ELEC 522. 2018. Advanced VLSI Design. https:\/\/www.clear.rice.edu\/elec522\/."},{"key":"e_1_3_2_1_3_1","unstructured":"ESE 532. 2018. System-on-a-Chip Architecture. https:\/\/www.seas.upenn.edu\/~ese532\/.  ESE 532. 2018. System-on-a-Chip Architecture. https:\/\/www.seas.upenn.edu\/~ese532\/."},{"key":"e_1_3_2_1_4_1","unstructured":"ECE 5775. 2018. High-Level Digital Design Automation. https:\/\/www.csl.cornell.edu\/courses\/ece5775\/.  ECE 5775. 2018. High-Level Digital Design Automation. https:\/\/www.csl.cornell.edu\/courses\/ece5775\/."},{"key":"e_1_3_2_1_5_1","unstructured":"CSE 599s. 2018. Hardware\/Software Co-Optimization for Machine Learning. https:\/\/courses.cs.washington.edu\/courses\/cse599s\/18sp\/.  CSE 599s. 2018. Hardware\/Software Co-Optimization for Machine Learning. https:\/\/courses.cs.washington.edu\/courses\/cse599s\/18sp\/."},{"key":"e_1_3_2_1_6_1","unstructured":"MIT 6.375. 2016. Complex Digital Systems. http:\/\/csg.csail.mit.edu\/6.375\/.  MIT 6.375. 2016. Complex Digital Systems. http:\/\/csg.csail.mit.edu\/6.375\/."},{"key":"e_1_3_2_1_7_1","unstructured":"ECE 643. 2017. Reconfigurable Logic - Technology Architecture and Applications. http:\/\/users.ece.cmu.edu\/~jhoe\/course\/ece643\/.  ECE 643. 2017. Reconfigurable Logic - Technology Architecture and Applications. http:\/\/users.ece.cmu.edu\/~jhoe\/course\/ece643\/."},{"key":"e_1_3_2_1_8_1","unstructured":"ARM. 2018. AMBA AXI and ACE Protocol Specification. http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.ihi0022d\/.  ARM. 2018. AMBA AXI and ACE Protocol Specification. http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.ihi0022d\/."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2013.6566706"},{"key":"e_1_3_2_1_10_1","unstructured":"B. Bailey etal 2010. TLM-driven Design and Verification Methodology. Lulu Enterprises.  B. Bailey et al. 2010. TLM-driven Design and Verification Methodology. Lulu Enterprises."},{"key":"e_1_3_2_1_11_1","unstructured":"K. Barker etal 2013. PERFECT (Power Efficiency Revolution For Embedded Computing Technologies) Benchmark Suite Manual. PNNL and GTRI. http:\/\/hpc.pnnl.gov\/perfect.  K. Barker et al. 2013. PERFECT (Power Efficiency Revolution For Embedded Computing Technologies) Benchmark Suite Manual. PNNL and GTRI. http:\/\/hpc.pnnl.gov\/perfect."},{"volume-title":"SystemC: From the Ground Up","author":"Black C.","key":"e_1_3_2_1_12_1","unstructured":"David C. Black , Jack Donovan, Bill Bunton, and Anna Keist. 2009. SystemC: From the Ground Up , Second Edition. Springer . David C. Black, Jack Donovan, Bill Bunton, and Anna Keist. 2009. SystemC: From the Ground Up, Second Edition. Springer."},{"key":"e_1_3_2_1_13_1","unstructured":"Bloomberg News. 2018. Facebook To Design Own Chips Cut Back On Intel Qualcomm Reliance. https:\/\/www.investors.com\/news\/technology\/facebook-building-chips\/.  Bloomberg News. 2018. Facebook To Design Own Chips Cut Back On Intel Qualcomm Reliance. https:\/\/www.investors.com\/news\/technology\/facebook-building-chips\/."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/N-SSC.2007.4785534"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941487.1941507"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2480849"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2905018"},{"volume-title":"Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD). 309--315","author":"Carloni L. P.","key":"e_1_3_2_1_18_1","unstructured":"L. P. Carloni , K. L. McMillan , A. Saldanha , and A. L. Sangiovanni-Vincentelli . 1999. A Methodology for \"Correct-by-Construction\" Latency Insensitive Design . In Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD). 309--315 . L. P. Carloni, K. L. McMillan, A. Saldanha, and A. L. Sangiovanni-Vincentelli. 1999. A Methodology for \"Correct-by-Construction\" Latency Insensitive Design. In Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD). 309--315."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.945302"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/944645.944666"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195647"},{"key":"e_1_3_2_1_22_1","volume-title":"Proc. IEEE 100","author":"Cavin R. K.","year":"2012","unstructured":"R. K. Cavin , P. Lugli , and V. V. Zhirnov . 2012. Science and Engineering Beyond Moore's Law . Proc. IEEE 100 , Special Centennial Issue ( May 2012 ), 1720--1749. R. K. Cavin, P. Lugli, and V. V. Zhirnov. 2012. Science and Engineering Beyond Moore's Law. Proc. IEEE 100, Special Centennial Issue (May 2012), 1720--1749."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2008914"},{"key":"e_1_3_2_1_24_1","first-page":"12","article-title":"End of Moore's law","volume":"46","author":"Colwell R.","year":"2013","unstructured":"R. Colwell . 2013 . End of Moore's law . IEEE Computer 46 , 12 (Dec. 2013), 49. R. Colwell. 2013. End of Moore's law. IEEE Computer 46, 12 (Dec. 2013), 49.","journal-title":"IEEE Computer"},{"edition":"3","volume-title":"Linux Device Drivers","key":"e_1_3_2_1_25_1","unstructured":"Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman. 2005. Linux Device Drivers , 3 rd Edition. O'Reilly Media, Inc. Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman. 2005. Linux Device Drivers, 3rd Edition. O'Reilly Media, Inc."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744794"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"S. Damaraju etal 2012. A 22nm IA Multi-CPU and GPU System-on-Chip. In ISSCC Digest of Technical Papers. 56--57.  S. Damaraju et al. 2012. A 22nm IA Multi-CPU and GPU System-on-Chip. In ISSCC Digest of Technical Papers. 56--57.","DOI":"10.1109\/ISSCC.2012.6176876"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2007.371249"},{"key":"e_1_3_2_1_29_1","unstructured":"EE382M.20. 2018. System-on-Chip Design (EE382M.20). http:\/\/users.ece.utexas.edu\/~gerstl\/ee382m_f18\/.  EE382M.20. 2018. System-on-Chip Design (EE382M.20). http:\/\/users.ece.utexas.edu\/~gerstl\/ee382m_f18\/."},{"volume-title":"High-Level Synthesis Blue Book","key":"e_1_3_2_1_30_1","unstructured":"Michael Fingeroff. 2010. High-Level Synthesis Blue Book . Mentor Graphics Corp . Michael Fingeroff. 2010. High-Level Synthesis Blue Book. Mentor Graphics Corp."},{"volume-title":"Transaction-Level Modeling with SystemC","author":"Ghenassia F.","key":"e_1_3_2_1_31_1","unstructured":"F. Ghenassia . 2006. Transaction-Level Modeling with SystemC . Springer . F. Ghenassia. 2006. Transaction-Level Modeling with SystemC. Springer."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2877288"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2017.162"},{"edition":"2","volume-title":"Digital Design and Computer Architecture","key":"e_1_3_2_1_34_1","unstructured":"David Harris and Sarah Harris. 2012. Digital Design and Computer Architecture ( 2 nd ed.). Morgan Kaufmann Publishers Inc . David Harris and Sarah Harris. 2012. Digital Design and Computer Architecture (2nd ed.). Morgan Kaufmann Publishers Inc."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3282307"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"crossref","unstructured":"M. Horowitz. 2014. Computing's Energy Problem (and What We Can Do About It). In ISSCC Digest of Technical Papers. 10--14.  M. Horowitz. 2014. Computing's Energy Problem (and What We Can Do About It). In ISSCC Digest of Technical Papers. 10--14.","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"e_1_3_2_1_37_1","unstructured":"IEEE. 2012. SystemC Standardization Working Group. 1666-2011 - IEEE Standard for Standard SystemC Reference Manual.  IEEE. 2012. SystemC Standardization Working Group. 1666-2011 - IEEE Standard for Standard SystemC Reference Manual."},{"key":"e_1_3_2_1_38_1","unstructured":"E. Jhonsa. 2018. Why Tech Giants Like Amazon Are Designing Their Own Chips -- And Who Benefits. https:\/\/www.thestreet.com\/opinion\/why-tech-giants-are-designing-their-own-chips-14807638.  E. Jhonsa. 2018. Why Tech Giants Like Amazon Are Designing Their Own Chips -- And Who Benefits. https:\/\/www.thestreet.com\/opinion\/why-tech-giants-are-designing-their-own-chips-14807638."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2018.8541473"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3199846"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.736561"},{"volume-title":"Compositional System-Level Design Exploration with Planning of High-Level Synthesis. In Conf. on Design, Automation and Test in Europe. 641--646","author":"Liu H.-Y.","key":"e_1_3_2_1_43_1","unstructured":"H.-Y. Liu , M. Petracca , and L. P. Carloni . 2012 . Compositional System-Level Design Exploration with Planning of High-Level Synthesis. In Conf. on Design, Automation and Test in Europe. 641--646 . H.-Y. Liu, M. Petracca, and L. P. Carloni. 2012. Compositional System-Level Design Exploration with Planning of High-Level Synthesis. In Conf. on Design, Automation and Test in Europe. 641--646."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.50"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897984"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/2968455.2968509"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.83"},{"key":"e_1_3_2_1_48_1","unstructured":"C. Metz. 2018. Amazon's Homegrown Chips Threaten Silicon Valley Giant Intel. https:\/\/www.nytimes.com\/2018\/12\/10\/technology\/amazon-server-chip-intel.html.  C. Metz. 2018. Amazon's Homegrown Chips Threaten Silicon Valley Giant Intel. https:\/\/www.nytimes.com\/2018\/12\/10\/technology\/amazon-server-chip-intel.html."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.24143"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"e_1_3_2_1_51_1","unstructured":"NVIDIA. 2018. NVDLA Primer. http:\/\/nvdla.org\/primer.html.  NVIDIA. 2018. NVDLA Primer. http:\/\/nvdla.org\/primer.html."},{"key":"e_1_3_2_1_52_1","unstructured":"Open SystemC Initiative (OSCI). {n.d.}. The SystemC Language Reference Manual. http:\/\/www.systemc.org\/.  Open SystemC Initiative (OSCI). {n.d.}. The SystemC Language Reference Manual. http:\/\/www.systemc.org\/."},{"key":"e_1_3_2_1_53_1","volume-title":"Hennessy","author":"Patterson A.","year":"2013","unstructured":"David A. Patterson and John L . Hennessy . 2013 . Computer Organization and Design: The Hardware\/Software Interface. Morgan Kaufmann Publishers Inc . David A. Patterson and John L. Hennessy. 2013. Computer Organization and Design: The Hardware\/Software Interface. Morgan Kaufmann Publishers Inc."},{"key":"e_1_3_2_1_54_1","volume-title":"Broadening the Exploration of the Accelerator Design Space in Embedded Scalable Platforms. In IEEE High Performance Extreme Computing Conference (HPEC). 1--7.","author":"Piccolboni L.","year":"2017","unstructured":"L. Piccolboni 2017 . Broadening the Exploration of the Accelerator Design Space in Embedded Scalable Platforms. In IEEE High Performance Extreme Computing Conference (HPEC). 1--7. L. Piccolboni et al. 2017. Broadening the Exploration of the Accelerator Design Space in Embedded Scalable Platforms. In IEEE High Performance Extreme Computing Conference (HPEC). 1--7."},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126566"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2611506"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2783680"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1177\/1094342004041291"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/2968456.2974004"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.890107"},{"volume-title":"Transaction-Accurate Interface Scheduling in High-Level Synthesis. In ESLsyn Conference. 31--36","author":"Sanguinetti J.","key":"e_1_3_2_1_61_1","unstructured":"J. Sanguinetti , M. Meredith , and S. Dart . 2012 . Transaction-Accurate Interface Scheduling in High-Level Synthesis. In ESLsyn Conference. 31--36 . J. Sanguinetti, M. Meredith, and S. Dart. 2012. Transaction-Accurate Interface Scheduling in High-Level Synthesis. In ESLsyn Conference. 31--36."},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISORC.2014.28"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.50"},{"volume-title":"Very Deep Convolutional Networks for Large-Scale Image Recognition. In Intl. Conf. on Learning Representations. 730--734","author":"Simonyan K.","key":"e_1_3_2_1_64_1","unstructured":"K. Simonyan and A. Zisserman . 2015 . Very Deep Convolutional Networks for Large-Scale Image Recognition. In Intl. Conf. on Learning Representations. 730--734 . K. Simonyan and A. Zisserman. 2015. Very Deep Convolutional Networks for Large-Scale Image Recognition. In Intl. Conf. on Learning Representations. 730--734."},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2005.387"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898030"}],"event":{"name":"ISCA '19: The 46th Annual International Symposium on Computer Architecture","sponsor":["IEEE","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Phoenix AZ USA","acronym":"ISCA '19"},"container-title":["Proceedings of the Workshop on Computer Architecture Education"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3338698.3338893","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3338698.3338893","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3338698.3338893","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:44:47Z","timestamp":1750203887000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3338698.3338893"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6,22]]},"references-count":66,"alternative-id":["10.1145\/3338698.3338893","10.1145\/3338698"],"URL":"https:\/\/doi.org\/10.1145\/3338698.3338893","relation":{},"subject":[],"published":{"date-parts":[[2019,6,22]]},"assertion":[{"value":"2019-06-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}