{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:30:33Z","timestamp":1750221033063,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,8,26]],"date-time":"2019-08-26T00:00:00Z","timestamp":1566777600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,8,26]]},"DOI":"10.1145\/3338852.3339865","type":"proceedings-article","created":{"date-parts":[[2019,10,2]],"date-time":"2019-10-02T12:28:55Z","timestamp":1570019335000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["An innovative strategy to reduce die area of robust OTA by using iMTGSPICE and diamond layout style for MOSFETs"],"prefix":"10.1145","author":[{"given":"Jos\u00e9 Roberto Banin","family":"J\u00fanior","sequence":"first","affiliation":[{"name":"FEI University Center, S\u00e3o B. do Campo, SP, Brazil"}]},{"given":"Rodrigo Alves","family":"de Lima Moreto","sequence":"additional","affiliation":[{"name":"FEI University Center, S\u00e3o B. do Campo, SP, Brazil"}]},{"given":"Gabriel Augusto","family":"da Silva","sequence":"additional","affiliation":[{"name":"FEI University Center, S\u00e3o B. do Campo, SP, Brazil"}]},{"given":"Carlos Eduardo","family":"Thomaz","sequence":"additional","affiliation":[{"name":"FEI University Center, S\u00e3o B. do Campo, SP, Brazil"}]},{"given":"Salvador Pinillos","family":"Gimenez","sequence":"additional","affiliation":[{"name":"FEI University Center, S\u00e3o B. do Campo, SP, Brazil"}]}],"member":"320","published-online":{"date-parts":[[2019,8,26]]},"reference":[{"issue":"3","key":"e_1_3_2_1_1_1","first-page":"108","article-title":"Random variability modeling and its impact on scaled CMOS circuits","volume":"9","author":"Gummalla Y. Y. S.","year":"2010","journal-title":"Journal of Computational Electronics"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2376987"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","unstructured":"R. P\u00f3voa I. Bastos N. Louren\u00e7o and N. Horta. 2016. Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques. Integration the VLSI Journal vol. 52 no. 1 pp. 243--252.  R. P\u00f3voa I. Bastos N. Louren\u00e7o and N. Horta. 2016. Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques. Integration the VLSI Journal vol. 52 no. 1 pp. 243--252.","DOI":"10.1016\/j.vlsi.2015.04.005"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.535416"},{"key":"e_1_3_2_1_5_1","unstructured":"C. A. C. Coello G. B. Lamont and D. A. V. Veldhuizen. 2007. Evolutionary Algorithms for Solving Multi-Objective Problems. NY: Springer-Verlag.  C. A. C. Coello G. B. Lamont and D. A. V. Veldhuizen. 2007. Evolutionary Algorithms for Solving Multi-Objective Problems. NY: Springer-Verlag."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"T. Tuma and A. B\u0171rmen. 2009. Circuit Simulation with SPICE OPUS Theory and Practice. Birkh\u00e4user Boston.  T. Tuma and A. B\u0171rmen. 2009. Circuit Simulation with SPICE OPUS Theory and Practice. Birkh\u00e4user Boston.","DOI":"10.1007\/978-0-8176-4867-1"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2661804"},{"key":"e_1_3_2_1_8_1","unstructured":"S. P. Gimenez. 2016. Layout Techniques for MOSFETs (ISBN: 9781627054881 | PDF ISBN: 9781627054829). 1\/1. ed. San Rafael California (USA).: Morgan & Claypool Publishers v. 1. 81p  S. P. Gimenez. 2016. Layout Techniques for MOSFETs (ISBN: 9781627054881 | PDF ISBN: 9781627054829). 1\/1. ed. San Rafael California (USA).: Morgan & Claypool Publishers v. 1. 81p"},{"key":"e_1_3_2_1_9_1","unstructured":"X. Liu L. Dai P. Li and S. Zou. 2018. Electrical performance of 130 nm PD-SOI MOSFET with diamond layout. Microelectronics Journal.  X. Liu L. Dai P. Li and S. Zou. 2018. Electrical performance of 130 nm PD-SOI MOSFET with diamond layout. Microelectronics Journal."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"S. P. Gimenez; E. H. S. Galembeck; C. Renaux and D. Flandre. 2015. Diamond layout style impact on SOI MOSFET in high temperature environment. Microelectronics and Reliability v. 55 p. 783\/MR11492-788.  S. P. Gimenez; E. H. S. Galembeck; C. Renaux and D. Flandre. 2015. Diamond layout style impact on SOI MOSFET in high temperature environment. Microelectronics and Reliability v. 55 p. 783\/MR11492-788.","DOI":"10.1016\/j.microrel.2015.02.015"},{"key":"e_1_3_2_1_11_1","first-page":"398","article-title":"Using diamond layout style to boost MOSFET frequency response of analogue IC","author":"Leoni S.P.","year":"2014","journal-title":"Electronics Letters"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"J. P. Colinge. 2004. Silicon-on-insulator techn. materials to VLSI. Kluwer Academic Publishers Boston MA USA.  J. P. Colinge. 2004. Silicon-on-insulator techn. materials to VLSI. Kluwer Academic Publishers Boston MA USA.","DOI":"10.1007\/978-1-4419-9106-5"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.1997.623701"},{"first-page":"1","volume-title":"2016 31st Symposium on Microelectronics Technology and Devices (SBMicro), Belo Horizonte","author":"Peruzzi V. V.","key":"e_1_3_2_1_14_1"},{"first-page":"1","volume-title":"Boosting the Performance of the Planar Power MOSFET By Using Diamond Layout Style. In: 29th Symposium on Microeletronics Technology and Devices, v. 1.","author":"da Silva G. A.","key":"e_1_3_2_1_15_1"},{"key":"e_1_3_2_1_16_1","first-page":"1618","article-title":"A compact Diamond MOSFET model accounting for the PAMDLE applicable down the 150 nm node","author":"Renaux S. P.","year":"2014","journal-title":"Electronics Letters"},{"key":"e_1_3_2_1_17_1","unstructured":"Spice Opus (c) version 2.31. Revision: 180. 2010. Circuit Simulator. Date Built: Jan 18 University of Ljubljana Slovenia. Faculty of Electrical Engineering. Group for Computer Aided Design. Available: http:\/\/www.spiceopus.si.  Spice Opus (c) version 2.31. Revision: 180. 2010. Circuit Simulator. Date Built: Jan 18 University of Ljubljana Slovenia. Faculty of Electrical Engineering. Group for Computer Aided Design. Available: http:\/\/www.spiceopus.si."},{"key":"e_1_3_2_1_18_1","first-page":"1","volume-title":"Proceedings of the SBCCI 2018, Bento Gon\u00e7alves, Rio Grande do Sul, Brazil, 2018. 31st Symposium on Integrated Circuits and Systems Design.","author":"Moreto R. A. L.","year":"2018"},{"volume-title":"Proc. of the 1st BRICS Countries Congress (BRICS-CCI), CI Applications in Industry Symposium","author":"Moreto R. A. L.","key":"e_1_3_2_1_19_1"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"crossref","unstructured":"R. A. L. Moreto. 2011. Projeto de um OTA CMOS por meio de um sistema evolucion\u00e1rio integrado ao SPICE 219 f. Disserta\u00e7\u00e3o (Mestrado em Engenharia El\u00e9trica) - Centro Universit\u00e1rio FEI S\u00e3o Bernardo do Campo.  R. A. L. Moreto. 2011. Projeto de um OTA CMOS por meio de um sistema evolucion\u00e1rio integrado ao SPICE 219 f. Disserta\u00e7\u00e3o (Mestrado em Engenharia El\u00e9trica) - Centro Universit\u00e1rio FEI S\u00e3o Bernardo do Campo.","DOI":"10.1590\/S0103-17592012000600004"},{"key":"e_1_3_2_1_21_1","unstructured":"2019. Taiwan Semiconductor Manufacturing Company (TSMC). [Online]. Available: https:\/\/www.tsmc.com\/english\/default.htm  2019. Taiwan Semiconductor Manufacturing Company (TSMC). [Online]. Available: https:\/\/www.tsmc.com\/english\/default.htm"}],"event":{"name":"SBCCI '19: 32nd Symposium on Integrated Circuits and Systems Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE Circuits & Systems Society"],"location":"S\u00e3o Paulo Brazil","acronym":"SBCCI '19"},"container-title":["Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3338852.3339865","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3338852.3339865","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T00:43:31Z","timestamp":1750207411000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3338852.3339865"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,8,26]]},"references-count":21,"alternative-id":["10.1145\/3338852.3339865","10.1145\/3338852"],"URL":"https:\/\/doi.org\/10.1145\/3338852.3339865","relation":{},"subject":[],"published":{"date-parts":[[2019,8,26]]},"assertion":[{"value":"2019-08-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}