{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T15:09:54Z","timestamp":1773414594629,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":12,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,8,26]],"date-time":"2019-08-26T00:00:00Z","timestamp":1566777600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,8,26]]},"DOI":"10.1145\/3338852.3339871","type":"proceedings-article","created":{"date-parts":[[2019,10,2]],"date-time":"2019-10-02T12:28:55Z","timestamp":1570019335000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["New insight for next generation SRAM"],"prefix":"10.1145","author":[{"given":"Adriana","family":"Arevalo","sequence":"first","affiliation":[{"name":"Universidad San Francisco de Quito, Quito, Ecuador"}]},{"given":"Romain","family":"Liautard","sequence":"additional","affiliation":[{"name":"INP ENSEEIHT, Toulouse, France"}]},{"given":"Daniel","family":"Romero","sequence":"additional","affiliation":[{"name":"Universidad San Francisco de Quito, Quito, Ecuador"}]},{"given":"Lionel","family":"Trojman","sequence":"additional","affiliation":[{"name":"Universidad San Francisco de Quito, Quito, Ecuador"}]},{"given":"Luis-Miguel","family":"Procel","sequence":"additional","affiliation":[{"name":"Universidad San Francisco de Quito, Quito, Ecuador"}]}],"member":"320","published-online":{"date-parts":[[2019,8,26]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-88497-4"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.883344"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2015.2392793"},{"key":"e_1_3_2_1_4_1","unstructured":"F. Settino etal (2017) Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog\/Mixed-Signal Circuits in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).  F. Settino et al. (2017) Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog\/Mixed-Signal Circuits in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2018.05.003"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2566614"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"M. D. V. Martino etal (2017) Experimental analysis of differential pairs designed with line tunnel FET devices in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).  M. D. V. Martino et al. (2017) Experimental analysis of differential pairs designed with line tunnel FET devices in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).","DOI":"10.1109\/S3S.2017.8308756"},{"key":"e_1_3_2_1_8_1","volume-title":"IEEE Symposium on Industrial Electronics & Applications.","author":"Dasgupta S.","year":"2009","unstructured":"Paridhi Athe and S. Dasgupta ( 2009 ), A comparative study of 6T, 8T and 9T decanano SRAM cell , in IEEE Symposium on Industrial Electronics & Applications. Paridhi Athe and S. Dasgupta (2009), A comparative study of 6T, 8T and 9T decanano SRAM cell, in IEEE Symposium on Industrial Electronics & Applications."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228414"},{"key":"e_1_3_2_1_10_1","unstructured":"Predictive Technology Model. Arizona State University. Accessed on Apr. 20 2018 Available: https:\/\/ptm.asu.edu.  Predictive Technology Model. Arizona State University. Accessed on Apr. 20 2018 Available: https:\/\/ptm.asu.edu."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2494845"},{"key":"e_1_3_2_1_12_1","volume-title":"Accessed on","author":"SYNOPSYS.","year":"2018","unstructured":"Custom Compiler. Datasheet. Assistants. SYNOPSYS. Accessed on : Apr. 20, 2018 , Available: https:\/\/www.synopsys.com. Custom Compiler. Datasheet. Assistants. SYNOPSYS. Accessed on: Apr. 20, 2018, Available: https:\/\/www.synopsys.com."}],"event":{"name":"SBCCI '19: 32nd Symposium on Integrated Circuits and Systems Design","location":"S\u00e3o Paulo Brazil","acronym":"SBCCI '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE Circuits & Systems Society"]},"container-title":["Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3338852.3339871","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3338852.3339871","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T00:26:20Z","timestamp":1750206380000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3338852.3339871"}},"subtitle":["tunnel FET versus FinFET for different topologies"],"short-title":[],"issued":{"date-parts":[[2019,8,26]]},"references-count":12,"alternative-id":["10.1145\/3338852.3339871","10.1145\/3338852"],"URL":"https:\/\/doi.org\/10.1145\/3338852.3339871","relation":{},"subject":[],"published":{"date-parts":[[2019,8,26]]},"assertion":[{"value":"2019-08-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}