{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:29:17Z","timestamp":1750220957344,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,5,24]],"date-time":"2019-05-24T00:00:00Z","timestamp":1558656000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,5,24]]},"DOI":"10.1145\/3339363.3339388","type":"proceedings-article","created":{"date-parts":[[2019,7,8]],"date-time":"2019-07-08T16:54:49Z","timestamp":1562604889000},"page":"102-107","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["The Study of Three Level Parallelisms in Ray Tracing Algorithm"],"prefix":"10.1145","author":[{"given":"Hui","family":"Wei","sequence":"first","affiliation":[{"name":"State Key Laboratory of High-End Server &amp; Storage Technology (Inspur Group Company Limited), Beijing, China"}]},{"given":"Yaqian","family":"Zhao","sequence":"additional","affiliation":[{"name":"State Key Laboratory of High-End Server &amp; Storage Technology (Inspur Group Company Limited), Beijing, China"}]},{"given":"Rengang","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory of High-End Server &amp; Storage Technology (Inspur Group Company Limited), Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2019,5,24]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2543651.2543673"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00371-018-1532-8"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1572769.1572792"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/3105762.3105773"},{"key":"e_1_3_2_1_5_1","volume-title":"Latency considerations of depth-first GPU ray tracing","author":"Guthe M.","year":"2014","unstructured":"Guthe , M. ( 2014 ). Latency considerations of depth-first GPU ray tracing . Guthe, M. (2014). Latency considerations of depth-first GPU ray tracing."},{"key":"e_1_3_2_1_6_1","volume-title":"High PERFORMANCE Graphics.","author":"Binder N.","year":"2016","unstructured":"Binder , N. and A. Keller ( 2016 ). Efficient stackless hierarchy traversal on GPUs with backtracking in constant time . In High PERFORMANCE Graphics. Binder, N. and A. Keller (2016). Efficient stackless hierarchy traversal on GPUs with backtracking in constant time. In High PERFORMANCE Graphics."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1111\/cgf.12259"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2461217.2461219"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/1921479.1921496"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1111\/j.1467-8659.2007.01064.x"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186822.1073211"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1058129.1058143"},{"key":"e_1_3_2_1_13_1","volume-title":"International Conference on Field-Programmable Technology.","author":"Lee J.","year":"2014","unstructured":"Lee , J. , et al. ( 2014 ). Real-time ray tracing on coarse-grained reconfigurable processor . In International Conference on Field-Programmable Technology. Lee, J., et al. (2014). Real-time ray tracing on coarse-grained reconfigurable processor. In International Conference on Field-Programmable Technology."},{"key":"e_1_3_2_1_14_1","volume-title":"Efficient Ray Tracing on FPGAs","author":"Collinson S.","year":"2014","unstructured":"Collinson , S. ( 2014 ). Efficient Ray Tracing on FPGAs . Collinson, S. (2014). Efficient Ray Tracing on FPGAs."},{"key":"e_1_3_2_1_15_1","unstructured":"xilinx. Xilinx FPGA&3D IC. Available from: https:\/\/china.xilinx.com\/products\/silicon-devices\/fpga.html.  xilinx. Xilinx FPGA&3D IC. Available from: https:\/\/china.xilinx.com\/products\/silicon-devices\/fpga.html."}],"event":{"name":"CSSE 2019: 2019 2nd International Conference on Computer Science and Software Engineering","sponsor":["Research Center for Science and Technology for Learning, National Central University, Taiwan"],"location":"Xi'an China","acronym":"CSSE 2019"},"container-title":["Proceedings of the 2nd International Conference on Computer Science and Software Engineering"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3339363.3339388","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3339363.3339388","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:54:07Z","timestamp":1750204447000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3339363.3339388"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5,24]]},"references-count":15,"alternative-id":["10.1145\/3339363.3339388","10.1145\/3339363"],"URL":"https:\/\/doi.org\/10.1145\/3339363.3339388","relation":{},"subject":[],"published":{"date-parts":[[2019,5,24]]},"assertion":[{"value":"2019-05-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}